target/riscv: rvv: Handle mask/source overlap of vector reduction instructions

[PATCH] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions

Anton Blanchard posted 1 patch 1 month, 1 week ago

Download mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260417120626.77415-1-antonb@tenstorrent.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
1 file changed, 2 insertions(+)

Expand all Fold all

[PATCH] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions

Posted by Anton Blanchard 1 month, 1 week ago

Masked vector reduction instructions must not use v0 as a source register.
Check rs1 and rs2 against the mask register when vm=0.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d9a0027e0b..6e8d32636e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3046,6 +3046,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           require_vm(a->vm, a->rs1) &&
+           require_vm(a->vm, a->rs2) &&
            vext_check_reduction(s, a->rs2);
 }
 
-- 
2.34.1

Re: [PATCH] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions

Posted by Alistair Francis 1 month ago

On Fri, Apr 17, 2026 at 10:08 PM Anton Blanchard <antonb@tenstorrent.com> wrote:
>
> Masked vector reduction instructions must not use v0 as a source register.
> Check rs1 and rs2 against the mask register when vm=0.
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index d9a0027e0b..6e8d32636e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3046,6 +3046,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
>  {
>      return require_rvv(s) &&
>             vext_check_isa_ill(s) &&
> +           require_vm(a->vm, a->rs1) &&
> +           require_vm(a->vm, a->rs2) &&
>             vext_check_reduction(s, a->rs2);
>  }
>
> --
> 2.34.1
>
>

Re: [PATCH] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions

Posted by Daniel Henrique Barboza 1 month, 1 week ago


On 4/17/2026 9:06 AM, Anton Blanchard wrote:
> Masked vector reduction instructions must not use v0 as a source register.
> Check rs1 and rs2 against the mask register when vm=0.
> 
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index d9a0027e0b..6e8d32636e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3046,6 +3046,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           require_vm(a->vm, a->rs1) &&
> +           require_vm(a->vm, a->rs2) &&
>              vext_check_reduction(s, a->rs2);
>   }
>