target/riscv: rvv: Handle source overlap of vector widening reduction instructions

[PATCH] target/riscv: rvv: Handle source overlap of vector widening reduction instructions

Posted by Anton Blanchard 1 month, 1 week ago

Widening reductions read vs2 as a vector of SEW elements and vs1[0] as a
scalar of 2*SEW. The ISA does not allow the same vector register to be read
with different EEWs, so they must not overlap.

vs1 is read as a scalar from element 0, so it is treated as a single vector
register (independent of LMUL) when checking overlap.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4df9a40b44..d9a0027e0b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3062,6 +3062,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
 static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) && (s->sew < MO_64) &&
+           !is_overlapped(a->rs1, 1, a->rs2, 1 << MAX(s->lmul, 0)) &&
            ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
 }
 
-- 
2.34.1

Re: [PATCH] target/riscv: rvv: Handle source overlap of vector widening reduction instructions

Posted by Michael Tokarev 5 days, 1 hour ago

On 17.04.2026 11:03, Anton Blanchard wrote:
> Widening reductions read vs2 as a vector of SEW elements and vs1[0] as a
> scalar of 2*SEW. The ISA does not allow the same vector register to be read
> with different EEWs, so they must not overlap.
> 
> vs1 is read as a scalar from element 0, so it is treated as a single vector
> register (independent of LMUL) when checking overlap.
> 
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4df9a40b44..d9a0027e0b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3062,6 +3062,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
>   static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
>   {
>       return reduction_check(s, a) && (s->sew < MO_64) &&
> +           !is_overlapped(a->rs1, 1, a->rs2, 1 << MAX(s->lmul, 0)) &&
>              ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
>   }
>   

Shouldn't this change be in stable qemu series?
Or is it not important there?

I'm picking it up, please let me know if I shouldn't.

Thanks,

/mjt

Re: [PATCH] target/riscv: rvv: Handle source overlap of vector widening reduction instructions

Posted by Alistair Francis 2 weeks, 3 days ago

On Fri, Apr 17, 2026 at 6:06 PM Anton Blanchard <antonb@tenstorrent.com> wrote:
>
> Widening reductions read vs2 as a vector of SEW elements and vs1[0] as a
> scalar of 2*SEW. The ISA does not allow the same vector register to be read
> with different EEWs, so they must not overlap.
>
> vs1 is read as a scalar from element 0, so it is treated as a single vector
> register (independent of LMUL) when checking overlap.
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4df9a40b44..d9a0027e0b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3062,6 +3062,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
>  static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
>  {
>      return reduction_check(s, a) && (s->sew < MO_64) &&
> +           !is_overlapped(a->rs1, 1, a->rs2, 1 << MAX(s->lmul, 0)) &&
>             ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
>  }
>
> --
> 2.34.1
>
>

Re: [PATCH] target/riscv: rvv: Handle source overlap of vector widening reduction instructions

Posted by Alistair Francis 2 weeks, 3 days ago

On Fri, Apr 17, 2026 at 6:06 PM Anton Blanchard <antonb@tenstorrent.com> wrote:
>
> Widening reductions read vs2 as a vector of SEW elements and vs1[0] as a
> scalar of 2*SEW. The ISA does not allow the same vector register to be read
> with different EEWs, so they must not overlap.
>
> vs1 is read as a scalar from element 0, so it is treated as a single vector
> register (independent of LMUL) when checking overlap.

I assume this resolves https://gitlab.com/qemu-project/qemu/-/work_items/3208

>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4df9a40b44..d9a0027e0b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3062,6 +3062,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
>  static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
>  {
>      return reduction_check(s, a) && (s->sew < MO_64) &&
> +           !is_overlapped(a->rs1, 1, a->rs2, 1 << MAX(s->lmul, 0)) &&
>             ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
>  }
>
> --
> 2.34.1
>
>