[v2] target/riscv: A collection of bug fixes

[PATCH v2 0/4] target/riscv: A collection of bug fixes

alistair23@gmail.com posted 4 patches 1 month, 2 weeks ago

Diff against v1
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260415233740.3027321-1-alistair.francis@wdc.com

Maintainers: Laurent Vivier <laurent@vivier.eu>, Pierrick Bouvier <pierrick.bouvier@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/helper.h                   |  3 +++
target/riscv/csr.c                      |  8 ++++++++
target/riscv/op_helper.c                | 14 ++++++++++++++
target/riscv/vector_helper.c            |  9 ++++-----
target/riscv/insn_trans/trans_rva.c.inc |  6 ++++++
linux-user/strace.list                  |  4 ++--
6 files changed, 37 insertions(+), 7 deletions(-)

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[PATCH v2 0/4] target/riscv: A collection of bug fixes

Posted by alistair23@gmail.com 1 month, 2 weeks ago

From: Alistair Francis <alistair.francis@wdc.com>

This is a collection of patches to fix a few of the open RISC-V bugs [1].

1: https://gitlab.com/qemu-project/qemu/-/work_items?first_page_size=20&label_name%5B%5D=target%3A%20riscv&sort=created_date&state=opened

v2:
 - Drop merged patches
 - Fixup typos
 - Removed read/write syscall print functions and use %p instead
 - Rework "Don't OR mip.SEIP when mvien is one" patch

Alistair Francis (4):
  target/riscv: Generate access fault if sc comparison fails
  linux-user/strace: Use pointer type for read and write values
  target/riscv: Don't OR mip.SEIP when mvien is one
  target/riscv: Use ELEN for Fractional LMUL check

 target/riscv/helper.h                   |  3 +++
 target/riscv/csr.c                      |  8 ++++++++
 target/riscv/op_helper.c                | 14 ++++++++++++++
 target/riscv/vector_helper.c            |  9 ++++-----
 target/riscv/insn_trans/trans_rva.c.inc |  6 ++++++
 linux-user/strace.list                  |  4 ++--
 6 files changed, 37 insertions(+), 7 deletions(-)

-- 
2.53.0

Re: [PATCH v2 0/4] target/riscv: A collection of bug fixes

Posted by Alistair Francis 1 month ago

On Thu, Apr 16, 2026 at 9:38 AM <alistair23@gmail.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> This is a collection of patches to fix a few of the open RISC-V bugs [1].
>
> 1: https://gitlab.com/qemu-project/qemu/-/work_items?first_page_size=20&label_name%5B%5D=target%3A%20riscv&sort=created_date&state=opened
>
> v2:
>  - Drop merged patches
>  - Fixup typos
>  - Removed read/write syscall print functions and use %p instead
>  - Rework "Don't OR mip.SEIP when mvien is one" patch
>
> Alistair Francis (4):
>   target/riscv: Generate access fault if sc comparison fails
>   linux-user/strace: Use pointer type for read and write values
>   target/riscv: Don't OR mip.SEIP when mvien is one
>   target/riscv: Use ELEN for Fractional LMUL check

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/helper.h                   |  3 +++
>  target/riscv/csr.c                      |  8 ++++++++
>  target/riscv/op_helper.c                | 14 ++++++++++++++
>  target/riscv/vector_helper.c            |  9 ++++-----
>  target/riscv/insn_trans/trans_rva.c.inc |  6 ++++++
>  linux-user/strace.list                  |  4 ++--
>  6 files changed, 37 insertions(+), 7 deletions(-)
>
> --
> 2.53.0
>