[RFC PATCH v5 0/6] target/mips: Translate MSA vector load/store opcodes

Philippe Mathieu-Daudé posted 6 patches 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260415202027.83008-1-philmd@linaro.org
Maintainers: "Philippe Mathieu-Daudé" <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <arikalo@gmail.com>
target/mips/tcg/msa_helper.h.inc |   9 --
target/mips/tcg/msa_helper.c     | 176 -------------------------------
target/mips/tcg/msa_translate.c  |  93 +++++++++++++---
3 files changed, 81 insertions(+), 197 deletions(-)
[RFC PATCH v5 0/6] target/mips: Translate MSA vector load/store opcodes
Posted by Philippe Mathieu-Daudé 2 weeks ago
Since v4:
- No algorithm change
- Split to ease review

Hi Richard,

I tried to implement your suggestion from v3 [*]. Unfortunately
the box where I had the MSA test suite got erased, so it will
take me some time to restore the setup. I was surprised these
patches pass our CI tests so I added a pair of abort() which
didn't fire, so this code path isn't tested at all there.
Anyhow, do you mind having a quick look to see this is going
in the right direction?

Thanks!

Phil.

[*] https://lore.kernel.org/qemu-devel/2680c481-088b-4366-abc3-7d48d90db0b5@linaro.org/

Philippe Mathieu-Daudé (6):
  target/mips: Expand TRANS_DF_iv() macro for MSA Load/Store
  target/mips: Convert MSA LD/ST.B (Byte Vector)
  target/mips: Convert MSA LD/ST.H (Halfword Vector)
  target/mips: Convert MSA LD/ST.W (Word Vector)
  target/mips: Convert MSA LD/ST.D (Doubleword Vector)
  target/mips: Endian-swap MSA LD/ST.D (Doubleword Vector)

 target/mips/tcg/msa_helper.h.inc |   9 --
 target/mips/tcg/msa_helper.c     | 176 -------------------------------
 target/mips/tcg/msa_translate.c  |  93 +++++++++++++---
 3 files changed, 81 insertions(+), 197 deletions(-)

-- 
2.53.0