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[PATCH] hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node

Vivien LEGER posted 1 patch 1 month, 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260411154535.1451361-1-vivien.leger@gmail.com
Maintainers: Bernhard Beschow <shentey@gmail.com>
hw/ppc/e500.c      | 2 +-
hw/ppc/e500.h      | 1 +
hw/ppc/e500plat.c  | 1 +
hw/ppc/mpc8544ds.c | 1 +
4 files changed, 4 insertions(+), 1 deletion(-)
[PATCH] hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node
Posted by Vivien LEGER 1 month, 2 weeks ago 
The bus-frequency property in the CPU FDT node was hardcoded to 0.
This is incorrect - it should reflect the actual platform bus clock
frequency, as firmware and RTOSes use it to derive peripheral clock
rates.

Notably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC
global timer interval. With bus-frequency=0, the timer interval
overflows to ~85 seconds, preventing any clock interrupts from firing.

Fix by adding a bus_freq field to PPCE500MachineClass and using it in
the FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for
existing machines, matching the existing clock_freq value.

Signed-off-by: Vivien LEGER <vivien.leger@gmail.com>
---
 hw/ppc/e500.c      | 2 +-
 hw/ppc/e500.h      | 1 +
 hw/ppc/e500plat.c  | 1 +
 hw/ppc/mpc8544ds.c | 1 +
 4 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index d6ca2e8..5be2f20 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -518,7 +518,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
                               env->icache_line_size);
         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
-        qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
+        qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", pmc->bus_freq);
         if (cpu->cpu_index) {
             qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
             qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 11f8ae5..6d56c7b 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -40,6 +40,7 @@ struct PPCE500MachineClass {
     hwaddr pci_mmio_bus_base;
     hwaddr spin_base;
     uint32_t clock_freq;
+    uint32_t bus_freq;
     uint32_t tb_freq;
 };
 
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index ca56472..85cec81 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -94,6 +94,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data)
     pmc->pci_mmio_bus_base = 0xE0000000ULL;
     pmc->spin_base = 0xFEF000000ULL;
     pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
+    pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;
     pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
 
     mc->desc = "generic paravirt e500 platform";
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 5826985..d022761 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -56,6 +56,7 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data)
     pmc->pci_pio_base = 0xE1000000ULL;
     pmc->spin_base = 0xEF000000ULL;
     pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
+    pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;
     pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
 
     mc->desc = "mpc8544ds";
-- 
2.53.0
Re: [PATCH] hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node
Posted by Bernhard Beschow 1 month, 2 weeks ago 
+ qemu-stable

Am 11. April 2026 15:45:35 UTC schrieb Vivien LEGER <vivien.leger@gmail.com>:
>The bus-frequency property in the CPU FDT node was hardcoded to 0.
>This is incorrect - it should reflect the actual platform bus clock
>frequency, as firmware and RTOSes use it to derive peripheral clock
>rates.
>
>Notably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC
>global timer interval. With bus-frequency=0, the timer interval
>overflows to ~85 seconds, preventing any clock interrupts from firing.
>
>Fix by adding a bus_freq field to PPCE500MachineClass and using it in
>the FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for
>existing machines, matching the existing clock_freq value.
>
>Signed-off-by: Vivien LEGER <vivien.leger@gmail.com>
>---
> hw/ppc/e500.c      | 2 +-
> hw/ppc/e500.h      | 1 +
> hw/ppc/e500plat.c  | 1 +
> hw/ppc/mpc8544ds.c | 1 +
> 4 files changed, 4 insertions(+), 1 deletion(-)
>
>diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
>index d6ca2e8..5be2f20 100644
>--- a/hw/ppc/e500.c
>+++ b/hw/ppc/e500.c
>@@ -518,7 +518,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
>                               env->icache_line_size);
>         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
>         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
>-        qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
>+        qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", pmc->bus_freq);
>         if (cpu->cpu_index) {
>             qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
>             qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
>diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
>index 11f8ae5..6d56c7b 100644
>--- a/hw/ppc/e500.h
>+++ b/hw/ppc/e500.h
>@@ -40,6 +40,7 @@ struct PPCE500MachineClass {
>     hwaddr pci_mmio_bus_base;
>     hwaddr spin_base;
>     uint32_t clock_freq;
>+    uint32_t bus_freq;
>     uint32_t tb_freq;
> };
> 
>diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
>index ca56472..85cec81 100644
>--- a/hw/ppc/e500plat.c
>+++ b/hw/ppc/e500plat.c
>@@ -94,6 +94,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data)
>     pmc->pci_mmio_bus_base = 0xE0000000ULL;
>     pmc->spin_base = 0xFEF000000ULL;
>     pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
>+    pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;
>     pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
> 
>     mc->desc = "generic paravirt e500 platform";
>diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
>index 5826985..d022761 100644
>--- a/hw/ppc/mpc8544ds.c
>+++ b/hw/ppc/mpc8544ds.c
>@@ -56,6 +56,7 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data)
>     pmc->pci_pio_base = 0xE1000000ULL;
>     pmc->spin_base = 0xEF000000ULL;
>     pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
>+    pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;
>     pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
> 
>     mc->desc = "mpc8544ds";

Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Re: [PATCH] hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node
Posted by Michael Tokarev 3 weeks, 4 days ago 
On 13.04.2026 14:30, Bernhard Beschow wrote:
> + qemu-stable

Hi!

A bit late reply, but here it goes.

What do you recommend for 10.0.x series and this patch?
This change (commit 774e6f5c15) contextually depends on a
previous commit in the same area, v10.0.0-1542-gea585b1022
"hw/ppc/e500: Move clock and TB frequency to machine class".

Should I pick both to 10.0.x, or neither, or modify 774e6f5c15
to apply without ea585b1022?  Do these patches have effect on
migration stream?

What do yo think?

Thanks,

/mjt

> Am 11. April 2026 15:45:35 UTC schrieb Vivien LEGER <vivien.leger@gmail.com>:
>> The bus-frequency property in the CPU FDT node was hardcoded to 0.
>> This is incorrect - it should reflect the actual platform bus clock
>> frequency, as firmware and RTOSes use it to derive peripheral clock
>> rates.
>>
>> Notably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC
>> global timer interval. With bus-frequency=0, the timer interval
>> overflows to ~85 seconds, preventing any clock interrupts from firing.
>>
>> Fix by adding a bus_freq field to PPCE500MachineClass and using it in
>> the FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for
>> existing machines, matching the existing clock_freq value.
>>
>> Signed-off-by: Vivien LEGER <vivien.leger@gmail.com>
>> ---
>> hw/ppc/e500.c      | 2 +-
>> hw/ppc/e500.h      | 1 +
>> hw/ppc/e500plat.c  | 1 +
>> hw/ppc/mpc8544ds.c | 1 +
>> 4 files changed, 4 insertions(+), 1 deletion(-)

Patchew 2.1-devel-ea86937

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