target/riscv: fix RV32 henvcfg/stateen CSR handling

[PATCH 0/2] target/riscv: fix RV32 henvcfg/stateen CSR handling

Posted by Bruno Sa 1 day, 23 hours ago

This series fixes two RV32-specific CSR handling issues in target/riscv.

The first patch fixes write_henvcfg() so that an RV32 write to henvcfg
does not clear the upper-half bits implemented in henvcfgh.

The second patch fixes the RV32 split handling of the stateen CSRs by
rejecting the xH CSRs on RV64, placing the upper-half mask bits in the
*stateen0h write paths on RV32, and dropping the unsupported writable
bits from sstateen0.

Bruno Sa (2):
  target/riscv: preserve RV32 henvcfgh on henvcfg writes
  target/riscv: fix RV32 stateen CSR handling

 target/riscv/csr.c | 122 ++++++++++++++++++++++++++++++++-------------
 1 file changed, 86 insertions(+), 36 deletions(-)

-- 
2.43.0

Re: [PATCH 0/2] target/riscv: fix RV32 henvcfg/stateen CSR handling

Posted by Alistair Francis 1 day, 14 hours ago

On Fri, Apr 10, 2026 at 3:27 AM Bruno Sa <bruno.vilaca.sa@gmail.com> wrote:
>
> This series fixes two RV32-specific CSR handling issues in target/riscv.
>
> The first patch fixes write_henvcfg() so that an RV32 write to henvcfg
> does not clear the upper-half bits implemented in henvcfgh.
>
> The second patch fixes the RV32 split handling of the stateen CSRs by
> rejecting the xH CSRs on RV64, placing the upper-half mask bits in the
> *stateen0h write paths on RV32, and dropping the unsupported writable
> bits from sstateen0.
>
> Bruno Sa (2):
>   target/riscv: preserve RV32 henvcfgh on henvcfg writes
>   target/riscv: fix RV32 stateen CSR handling

Thanks for the patches.

I have applied patch 1 to my tree, but patch 2 doesn't seem to apply.
Do you mind rebasing it on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
resending a v2

Alistair

>
>  target/riscv/csr.c | 122 ++++++++++++++++++++++++++++++++-------------
>  1 file changed, 86 insertions(+), 36 deletions(-)
>
> --
> 2.43.0
>