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[PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes

Vivian Wang posted 5 patches 2 days, 10 hours ago
Maintainers: Peter Maydell <peter.maydell@linaro.org>, Leif Lindholm <leif.lindholm@oss.qualcomm.com>, Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Paul Burton <paulburton@kernel.org>, Aleksandar Rikalo <arikalo@gmail.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Jia Liu <proljc@gmail.com>, Stafford Horne <shorne@gmail.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>
[PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes
Posted by Vivian Wang 2 days, 10 hours ago 
These unit addresses should have been in hex, not decimal, as per de
facto convention [1]. Fix them.

Link: https://lore.kernel.org/devicetree-spec/CAL_JsqJFv3+UJ-bjLGk0i7Wc+spsowCrqQZ_s3P4gN8r1W-Q-w@mail.gmail.com/ # [1]
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
---
 hw/riscv/sifive_u.c | 9 +++++----
 hw/riscv/spike.c    | 4 ++--
 hw/riscv/virt.c     | 4 ++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7ec67b2565..54f3bcc3b2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -168,8 +168,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
 
     for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
         int cpu_phandle = phandle++;
-        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
-        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
+        nodename = g_strdup_printf("/cpus/cpu@%x", (unsigned)cpu);
+        char *intc = g_strdup_printf("/cpus/cpu@%x/interrupt-controller",
+                                     (unsigned)cpu);
         qemu_fdt_add_subnode(fdt, nodename);
         /* cpu 0 is the management hart that does not have mmu */
         if (cpu != 0) {
@@ -198,7 +199,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     cells =  g_new0(uint32_t, ms->smp.cpus * 4);
     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
         nodename =
-            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
+            g_strdup_printf("/cpus/cpu@%x/interrupt-controller", (unsigned)cpu);
         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
@@ -249,7 +250,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
         nodename =
-            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
+            g_strdup_printf("/cpus/cpu@%x/interrupt-controller", (unsigned)cpu);
         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
         /* cpu 0 is the management hart that does not have S-mode */
         if (cpu == 0) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 35c696f891..cac01ea1ff 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -105,8 +105,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
         for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
             cpu_phandle = phandle++;
 
-            cpu_name = g_strdup_printf("/cpus/cpu@%d",
-                s->soc[socket].hartid_base + cpu);
+            cpu_name = g_strdup_printf("/cpus/cpu@%" PRIx32,
+                s->soc[socket].hartid_base + (uint32_t)cpu);
             qemu_fdt_add_subnode(fdt, cpu_name);
             if (is_32_bit) {
                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a1c323e66d..42a83dd829 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -248,8 +248,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
 
         cpu_phandle = (*phandle)++;
 
-        cpu_name = g_strdup_printf("/cpus/cpu@%d",
-            s->soc[socket].hartid_base + cpu);
+        cpu_name = g_strdup_printf("/cpus/cpu@%" PRIx32,
+            s->soc[socket].hartid_base + (uint32_t)cpu);
         qemu_fdt_add_subnode(ms->fdt, cpu_name);
 
         if (satp_mode_max != -1) {

-- 
2.53.0
Re: [PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes
Posted by Alistair Francis 1 day, 17 hours ago 
On Thu, Apr 9, 2026 at 4:42 PM Vivian Wang <wangruikang@iscas.ac.cn> wrote:
>
> These unit addresses should have been in hex, not decimal, as per de
> facto convention [1]. Fix them.
>
> Link: https://lore.kernel.org/devicetree-spec/CAL_JsqJFv3+UJ-bjLGk0i7Wc+spsowCrqQZ_s3P4gN8r1W-Q-w@mail.gmail.com/ # [1]
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/sifive_u.c | 9 +++++----
>  hw/riscv/spike.c    | 4 ++--
>  hw/riscv/virt.c     | 4 ++--
>  3 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7ec67b2565..54f3bcc3b2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -168,8 +168,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
>
>      for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
>          int cpu_phandle = phandle++;
> -        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
> -        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
> +        nodename = g_strdup_printf("/cpus/cpu@%x", (unsigned)cpu);
> +        char *intc = g_strdup_printf("/cpus/cpu@%x/interrupt-controller",
> +                                     (unsigned)cpu);
>          qemu_fdt_add_subnode(fdt, nodename);
>          /* cpu 0 is the management hart that does not have mmu */
>          if (cpu != 0) {
> @@ -198,7 +199,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
>      cells =  g_new0(uint32_t, ms->smp.cpus * 4);
>      for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
>          nodename =
> -            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
> +            g_strdup_printf("/cpus/cpu@%x/interrupt-controller", (unsigned)cpu);
>          uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
>          cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
>          cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
> @@ -249,7 +250,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
>      cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
>      for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
>          nodename =
> -            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
> +            g_strdup_printf("/cpus/cpu@%x/interrupt-controller", (unsigned)cpu);
>          uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
>          /* cpu 0 is the management hart that does not have S-mode */
>          if (cpu == 0) {
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 35c696f891..cac01ea1ff 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -105,8 +105,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
>          for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
>              cpu_phandle = phandle++;
>
> -            cpu_name = g_strdup_printf("/cpus/cpu@%d",
> -                s->soc[socket].hartid_base + cpu);
> +            cpu_name = g_strdup_printf("/cpus/cpu@%" PRIx32,
> +                s->soc[socket].hartid_base + (uint32_t)cpu);
>              qemu_fdt_add_subnode(fdt, cpu_name);
>              if (is_32_bit) {
>                  qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index a1c323e66d..42a83dd829 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -248,8 +248,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
>
>          cpu_phandle = (*phandle)++;
>
> -        cpu_name = g_strdup_printf("/cpus/cpu@%d",
> -            s->soc[socket].hartid_base + cpu);
> +        cpu_name = g_strdup_printf("/cpus/cpu@%" PRIx32,
> +            s->soc[socket].hartid_base + (uint32_t)cpu);
>          qemu_fdt_add_subnode(ms->fdt, cpu_name);
>
>          if (satp_mode_max != -1) {
>
> --
> 2.53.0
>
>
Re: [PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes
Posted by Philippe Mathieu-Daudé 2 days, 7 hours ago 
On 9/4/26 08:40, Vivian Wang wrote:
> These unit addresses should have been in hex, not decimal, as per de
> facto convention [1]. Fix them.
> 
> Link: https://lore.kernel.org/devicetree-spec/CAL_JsqJFv3+UJ-bjLGk0i7Wc+spsowCrqQZ_s3P4gN8r1W-Q-w@mail.gmail.com/ # [1]
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
> ---
>   hw/riscv/sifive_u.c | 9 +++++----
>   hw/riscv/spike.c    | 4 ++--
>   hw/riscv/virt.c     | 4 ++--
>   3 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7ec67b2565..54f3bcc3b2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -168,8 +168,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
>   
>       for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
>           int cpu_phandle = phandle++;
> -        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
> -        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
> +        nodename = g_strdup_printf("/cpus/cpu@%x", (unsigned)cpu);
> +        char *intc = g_strdup_printf("/cpus/cpu@%x/interrupt-controller",
> +                                     (unsigned)cpu);

No need to cast to unsigned explicitly, otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Patchew 2.1-devel-ea86937

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