This is Part 2 of the Hexagon system emulation series.  It adds the
runtime helpers, CPU operations, and translation support needed for
full-system emulation of the Hexagon DSP.

This includes:
 - Software interrupt (SWI) and interrupt handling
 - TLB fill and permission checking
 - System register read/write support in TCG
 - Implicit sysreg writes and translation-block termination
 - Stack overflow exception support
 - Thread scheduling helpers (setprio, resched, resume)
 - k0 lock/unlock for kernel mode
 - idef-parser support for fFRAMECHECK
 - TCG overrides for system transfer instructions

Based on Part 1 v6.

Changes since v3:
 - Rebased onto Part 1 v6
 - Fixed idef-parser fFRAMECHECK implementation (Taylor)
 - Removed pkt_ends_tb from DisasContext, call pkt_ends_tb() directly (Taylor)
 - Changed t_sreg_new_value sizing from NUM_SREGS to
   HEX_SREG_GLB_START (Taylor)
 - Removed unnecessary tcg_gen_mov_tl sreg pre-copy in
   gen_start_packet(); no sreg writes are predicated (Taylor)
 - Added continue after STID/IMASK/IPENDAD writeback in
   gen_sreg_writes() to avoid redundant writeback (Taylor)
 - Moved hexagon_greg_read() declaration to correct commit (Taylor)
 - Fixed set_enable_mask/clear_enable_mask return type consistency (Taylor)
 - Added early return for globalregs==false in set_enable_mask and
   set_wait_mode (Taylor)
 - Fixed bare %x/%d format specifiers across multiple files, using
   PRIx32/PRIu32/TARGET_FMT_lx as appropriate (Taylor)
 - Fixed mid-block variable declarations (C89 style)
 - Removed invalid PRM section references from setprio/resched
   commit message (Taylor)
 - Renamed "Add TLB, k0 {un,}lock" to "Add k0 {un,}lock" (Taylor)
 - Moved cycle counter/pcycle/modify_ssr commits to Part 1
 - All cycle counter code properly guarded by
   ifndef CONFIG_USER_ONLY (Taylor)

Previous versions:
 - v3: https://lore.kernel.org/qemu-devel/20260311040758.1068731-1-brian.cain@oss.qualcomm.com/
 - v2: https://lore.kernel.org/qemu-devel/20250902034847.1948010-1-brian.cain@oss.qualcomm.com/
 - v1: https://lore.kernel.org/qemu-devel/20250301052845.1012069-1-brian.cain@oss.qualcomm.com/

Brian Cain (26):
  target/hexagon: Implement {c,}swi helpers
  target/hexagon: Implement iassign{r,w} helpers
  target/hexagon: Implement start/stop helpers, soft reset
  target/hexagon: Implement {g,s}etimask helpers
  target/hexagon: Implement wait helper
  target/hexagon: Implement get_exe_mode()
  target/hexagon: Implement hex_tlb_entry_get_perm()
  target/hexagon: Implement software interrupt
  target/hexagon: Implement stack overflow exception
  target/hexagon: Implement exec_interrupt, set_irq
  target/hexagon: Implement hexagon_tlb_fill()
  target/hexagon: Implement siad inst
  target/hexagon: Implement hexagon_resume_threads()
  target/hexagon: Implement setprio, resched
  target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()
  target/hexagon: extend hexagon_cpu_mmu_index() for sysemu
  target/hexagon: Decode trap1, rte as COF
  target/hexagon: Implement modify_ssr, resched, pending_interrupt
  target/hexagon: Add pkt_ends_tb to translation
  target/hexagon: Add next_PC, {s,g}reg writes
  target/hexagon: Add implicit sysreg writes
  target/hexagon: Define system, guest reg names
  target/hexagon: Add k0 {un,}lock
  target/hexagon: Add PC to raise_exception, use fTRAP() helper
  target/hexagon: Add TCG overrides for transfer insts
  target/hexagon: Add support for loadw_phys

Matheus Tavares Bernardino (2):
  target/hexagon: add simple cpu_exec_reset and pointer_wrap
  target/hexagon: Add guest reg reading functionality

 target/hexagon/cpu.h                        |  11 +
 target/hexagon/cpu_helper.h                 |   8 +
 target/hexagon/gen_tcg.h                    |   7 -
 target/hexagon/gen_tcg_sys.h                |  25 ++
 target/hexagon/helper.h                     |   6 +-
 target/hexagon/hexswi.h                     |  17 +
 target/hexagon/idef-parser/parser-helpers.h |   2 +
 target/hexagon/internal.h                   |   4 +
 target/hexagon/macros.h                     |   3 -
 target/hexagon/sys_macros.h                 |   7 +
 target/hexagon/translate.h                  |   5 +-
 target/hexagon/reg_fields_def.h.inc         |  11 +
 linux-user/hexagon/cpu_loop.c               |   7 +
 target/hexagon/cpu.c                        | 360 ++++++++++++++-
 target/hexagon/decode.c                     |  14 +
 target/hexagon/genptr.c                     |  18 +-
 target/hexagon/hexswi.c                     | 267 +++++++++++
 target/hexagon/idef-parser/parser-helpers.c |   9 +
 target/hexagon/op_helper.c                  | 462 +++++++++++++++++++-
 target/hexagon/translate.c                  | 225 +++++++++-
 target/hexagon/hex_common.py                |   3 +
 target/hexagon/idef-parser/idef-parser.y    |   3 +
 target/hexagon/imported/encode_pp.def       |   1 +
 target/hexagon/imported/ldst.idef           |   3 +
 24 files changed, 1425 insertions(+), 53 deletions(-)
 create mode 100644 target/hexagon/hexswi.h
 create mode 100644 target/hexagon/hexswi.c

-- 
2.34.1