This series tackles (most of) the rest of target/arm, especially tcg folder.

We extract tcg memory operation in a new header, with a new type representing
virtual addresses.

Initially, I went down the way to have a dynamic definition of TCGv, which
required much more boilerplate and runtime checks. After discussing with
Richard, I realized it was not needed, and that could simply split 32 and 64 bit
properly in different files instead. This approach will not work with other
architectures, requiring something else, but it's enough for target/arm.

Files left are:
- target/arm/tcg/mve_helper.c
- target/arm/tcg/m_helper.c
- target/arm/tcg/cpu32.c

v11
---

- update comments

v10
---

- extract patch for endianness handling in arm_disas_set_info
- added some comments

v9
--

- introduce aarch64_translate_code *before* adding parameter to translator_loop
- use TCG_TYPE_VA as address type for translator_loop
- remove inline marker on functions merged from arm_ldst.h to translate.c
- refactor arm_ldl_code/arm_lduw_code

v8
--

- make translate.c compilation unit common.

v7
--

- add parameter to translator_loop to indicate address type for current tb.
- remove TCGv from target/arm/tcg/translate.c

v6
--

- meson.build: extract decode files in separate variables and explicitly include
  them in user and system code. The duplication is now minimized: one instance
  for all system binaries, and one per user binary.

v5
--

- reimplemented what v0 did with new approach defining new tcg-op-mem header
- reapply all straightforward patches from v0
- only translate.c is left, but first want to validate that changes here are ok
  for maintainers before doing more.

v0
--

See original thread:
https://lore.kernel.org/qemu-devel/20260109053158.2800705-1-pierrick.bouvier@linaro.org/#t

Note about v1 -> v4
-------------------

- After v0 which was trying to do too many changes, v1 to v4 focused on smaller
  things, and all patches have been merged already.
  https://patchew.org/QEMU/20260219040150.2098396-1-pierrick.bouvier@linaro.org/

Pierrick Bouvier (21):
  include/tcg/tcg-op: extract memory operations to tcg-op-mem.h
  target/arm/translate.h: remove tcg-op.h include
  target/arm/tcg/translate.h: remove tcg-op-gvec.h include
  target/arm/tcg/translate.h: remove TARGET_AARCH64
  target/arm/tcg/translate-vfp.c: make compilation unit common
  target/arm/tcg/translate-neon.c: make compilation unit common
  target/arm/tcg/translate-mve.c: make compilation unit common
  target/arm/tcg/translate-m-nocp.c: make compilation unit common
  target/arm/tcg/op_helper.c: make compilation unit common
  target/arm/tcg/gengvec.c: make compilation unit common
  target/arm/tcg/translate.c: remove MO_TE usage
  target/arm/tcg/translate.c: replace target_ulong with uint32_t
  target/arm/tcg/translate.c: extract aarch64_translate_code()
  tcg/translator: add parameter to translator_loop for current addr type
  target/arm/tcg/translate.c: replace TCGv with TCGv_va
  target/arm/tcg/translate-a64.c: use translator_ldl_end instead of
    arm_ldl_code
  target/arm/tcg/arm_ldst.h: merge in translate.c
  target/arm/tcg/translate.c: replace translator_ldl_swap with
    translator_ldl_end
  target/arm/cpu.c: simplify endianness handling in arm_disas_set_info
  target/arm/tcg/translate.c: remove target_ulong
  target/arm/tcg/translate.c: make compilation unit common

 include/exec/translator.h        |   4 +-
 include/tcg/tcg-op-mem.h         | 126 +++++++++++++++++++++++++++++++
 include/tcg/tcg-op.h             | 100 +-----------------------
 target/arm/internals.h           |   2 +
 target/arm/tcg/arm_ldst.h        |  47 ------------
 target/arm/tcg/translate.h       |  14 +---
 accel/tcg/translate-all.c        |   1 -
 accel/tcg/translator.c           |   4 +-
 target/alpha/translate.c         |   3 +-
 target/arm/cpu.c                 |   6 +-
 target/arm/tcg/op_helper.c       |   1 -
 target/arm/tcg/stubs32.c         |  24 ++++++
 target/arm/tcg/translate-a64.c   |  17 ++++-
 target/arm/tcg/translate-sme.c   |   1 +
 target/arm/tcg/translate-sve.c   |   1 +
 target/arm/tcg/translate.c       |  73 +++++++++++-------
 target/avr/translate.c           |   3 +-
 target/hexagon/translate.c       |   3 +-
 target/hppa/translate.c          |   3 +-
 target/i386/tcg/translate.c      |   3 +-
 target/loongarch/tcg/translate.c |   3 +-
 target/m68k/translate.c          |   3 +-
 target/microblaze/translate.c    |   3 +-
 target/mips/tcg/translate.c      |   3 +-
 target/or1k/translate.c          |   3 +-
 target/ppc/translate.c           |   3 +-
 target/riscv/translate.c         |   3 +-
 target/rx/translate.c            |   3 +-
 target/s390x/tcg/translate.c     |   3 +-
 target/sh4/translate.c           |   3 +-
 target/sparc/translate.c         |   3 +-
 target/tricore/translate.c       |   3 +-
 target/xtensa/translate.c        |   3 +-
 target/arm/tcg/meson.build       |  57 ++++++++++----
 34 files changed, 304 insertions(+), 228 deletions(-)
 create mode 100644 include/tcg/tcg-op-mem.h
 create mode 100644 target/arm/tcg/stubs32.c

-- 
2.47.3

On Tue, 7 Apr 2026 at 23:22, Pierrick Bouvier
<pierrick.bouvier@linaro.org> wrote:
>
> This series tackles (most of) the rest of target/arm, especially tcg folder.
>
> We extract tcg memory operation in a new header, with a new type representing
> virtual addresses.
>
> Initially, I went down the way to have a dynamic definition of TCGv, which
> required much more boilerplate and runtime checks. After discussing with
> Richard, I realized it was not needed, and that could simply split 32 and 64 bit
> properly in different files instead. This approach will not work with other
> architectures, requiring something else, but it's enough for target/arm.
>
> Files left are:
> - target/arm/tcg/mve_helper.c
> - target/arm/tcg/m_helper.c
> - target/arm/tcg/cpu32.c
>
> v11
> ---
>
> - update comments

It looks like this is all fully reviewed, so I've applied it
to what will become my target-arm queue once 11.1 reopens
for development.

thanks
-- PMM

On 4/9/26 8:51 AM, Peter Maydell wrote:
> On Tue, 7 Apr 2026 at 23:22, Pierrick Bouvier
> <pierrick.bouvier@linaro.org> wrote:
>>
>> This series tackles (most of) the rest of target/arm, especially tcg folder.
>>
>> We extract tcg memory operation in a new header, with a new type representing
>> virtual addresses.
>>
>> Initially, I went down the way to have a dynamic definition of TCGv, which
>> required much more boilerplate and runtime checks. After discussing with
>> Richard, I realized it was not needed, and that could simply split 32 and 64 bit
>> properly in different files instead. This approach will not work with other
>> architectures, requiring something else, but it's enough for target/arm.
>>
>> Files left are:
>> - target/arm/tcg/mve_helper.c
>> - target/arm/tcg/m_helper.c
>> - target/arm/tcg/cpu32.c
>>
>> v11
>> ---
>>
>> - update comments
> 
> It looks like this is all fully reviewed, so I've applied it
> to what will become my target-arm queue once 11.1 reopens
> for development.
>

Excellent, thanks Peter!

> thanks
> -- PMM