This allows to get rid of TARGET_AARCH64, and helps with next patch
which will define at runtime tcg address type, by adding a second entry
point in a different source file.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/arm/internals.h | 2 ++
target/arm/tcg/stubs32.c | 7 +++++++
target/arm/tcg/translate-a64.c | 9 +++++++++
target/arm/tcg/translate.c | 19 +++++++++----------
4 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 8ec27508473..2850edcb198 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc);
void arm_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c
index c5a0bc61f47..3945dc49e5e 100644
--- a/target/arm/tcg/stubs32.c
+++ b/target/arm/tcg/stubs32.c
@@ -3,6 +3,7 @@
*/
#include "qemu/osdep.h"
+#include "target/arm/internals.h"
#include "target/arm/tcg/translate.h"
@@ -15,3 +16,9 @@ void a64_translate_init(void)
{
/* Don't initialize for 32 bits. Call site will be fixed later. */
}
+
+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc)
+{
+ g_assert_not_reached();
+}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 35ad7530c4b..7533a4d01b6 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
#include "exec/target_page.h"
+#include "exec/translator.h"
#include "helper-a64.h"
#include "helper-sme.h"
#include "helper-sve.h"
@@ -10949,3 +10950,11 @@ const TranslatorOps aarch64_translator_ops = {
.translate_insn = aarch64_tr_translate_insn,
.tb_stop = aarch64_tr_tb_stop,
};
+
+void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,
+ int *max_insns, vaddr pc, void *host_pc)
+{
+ DisasContext dc = {};
+ translator_loop(cpu, tb, max_insns, pc, host_pc,
+ &aarch64_translator_ops, &dc.base);
+}
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 204f9657993..9ab926b118e 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -28,6 +28,7 @@
#include "semihosting/semihost.h"
#include "cpregs.h"
#include "exec/target_page.h"
+#include "exec/translator.h"
#include "helper.h"
#include "helper-mve.h"
@@ -6878,18 +6879,16 @@ static const TranslatorOps thumb_translator_ops = {
void arm_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
- DisasContext dc = { };
- const TranslatorOps *ops = &arm_translator_ops;
CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);
- if (EX_TBFLAG_AM32(tb_flags, THUMB)) {
- ops = &thumb_translator_ops;
- }
-#ifdef TARGET_AARCH64
if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {
- ops = &aarch64_translator_ops;
+ aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);
+ } else {
+ DisasContext dc = { };
+ translator_loop(cpu, tb, max_insns, pc, host_pc,
+ (EX_TBFLAG_AM32(tb_flags, THUMB)
+ ? &thumb_translator_ops
+ : &arm_translator_ops),
+ &dc.base);
}
-#endif
-
- translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);
}
--
2.47.3