target/riscv: A collection of bug fixes

[PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check

Posted by alistair23@gmail.com 4 days, 14 hours ago

From: Alistair Francis <alistair.francis@wdc.com>

The RISC-V spec states that

"""
For a given supported fractional LMUL setting, implementations
must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
"""

We were previously checking VLEN, instead of ELEN, so let's update to
check ELEN instead of VLEN for fractional scaling.

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 83dd26314d..b4fc791eb7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     target_ulong reserved = s2 &
                             MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
-    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;
 
     if (vlmul & 4) {
         /*
          * Fractional LMUL, check:
          *
-         * VLEN * LMUL >= SEW
-         * VLEN >> (8 - lmul) >= sew
-         * (vlenb << 3) >> (8 - lmul) >= sew
+         * ELEN * LMUL >= SEW
+         * ELEN >> (8 - vlmul) >= sew
          */
-        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
+        if (vlmul == 4 ||
+            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
             vill = true;
         }
     }
-- 
2.53.0

Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check

Posted by Chao Liu 3 days, 15 hours ago

On Tue, Apr 07, 2026 at 02:36:14PM +1000, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The RISC-V spec states that
> 
> """
> For a given supported fractional LMUL setting, implementations
> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
> """
> 
> We were previously checking VLEN, instead of ELEN, so let's update to
> check ELEN instead of VLEN for fractional scaling.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao
> ---
>  target/riscv/vector_helper.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 83dd26314d..b4fc791eb7 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>      target_ulong reserved = s2 &
>                              MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                              xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> -    uint16_t vlen = cpu->cfg.vlenb << 3;
>      int8_t lmul;
>  
>      if (vlmul & 4) {
>          /*
>           * Fractional LMUL, check:
>           *
> -         * VLEN * LMUL >= SEW
> -         * VLEN >> (8 - lmul) >= sew
> -         * (vlenb << 3) >> (8 - lmul) >= sew
> +         * ELEN * LMUL >= SEW
> +         * ELEN >> (8 - vlmul) >= sew
>           */
> -        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
> +        if (vlmul == 4 ||
> +            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
>              vill = true;
>          }
>      }
> -- 
> 2.53.0
>

Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check

Posted by LIU Zhiwei 4 days, 6 hours ago

Hi Alistair,

On 4/7/26 12:36 PM, alistair23@gmail.com wrote:
> From: Alistair Francis<alistair.francis@wdc.com>
>
> The RISC-V spec states that
>
> """
> For a given supported fractional LMUL setting, implementations
> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
> """

I think the meaning  of "must support"  in specification is "must at 
least support" instead of "must only support".

Sail or Spike have the same check as this patch to prevent user program 
can run on them, but
can't run on RTLs, as RTLs implementation may support SEW besides the 
SEWMIN and LMUL * ELEN range.

We can refer to discussion here: 
https://github.com/riscv-software-src/riscv-isa-sim/pull/620

In my opinion, we had better add a option such as "frac_sew_check" to 
make user set right value for their RTL implementation.

Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Thanks,
Zhiwei

> We were previously checking VLEN, instead of ELEN, so let's update to
> check ELEN instead of VLEN for fractional scaling.
>
> Resolves:https://gitlab.com/qemu-project/qemu/-/work_items/3196
> Signed-off-by: Alistair Francis<alistair.francis@wdc.com>
> ---
>   target/riscv/vector_helper.c | 9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 83dd26314d..b4fc791eb7 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>       target_ulong reserved = s2 &
>                               MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                               xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> -    uint16_t vlen = cpu->cfg.vlenb << 3;
>       int8_t lmul;
>   
>       if (vlmul & 4) {
>           /*
>            * Fractional LMUL, check:
>            *
> -         * VLEN * LMUL >= SEW
> -         * VLEN >> (8 - lmul) >= sew
> -         * (vlenb << 3) >> (8 - lmul) >= sew
> +         * ELEN * LMUL >= SEW
> +         * ELEN >> (8 - vlmul) >= sew
>            */
> -        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
> +        if (vlmul == 4 ||
> +            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
>               vill = true;
>           }
>       }

Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check

Posted by Alistair Francis 2 days, 13 hours ago

On Tue, Apr 7, 2026 at 10:13 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> Hi Alistair,
>
> On 4/7/26 12:36 PM, alistair23@gmail.com wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The RISC-V spec states that
>
> """
> For a given supported fractional LMUL setting, implementations
> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
> """
>
> I think the meaning  of "must support"  in specification is "must at least support" instead of "must only support".

Good point, I didn't really think about that.

>
> Sail or Spike have the same check as this patch to prevent user program can run on them, but
> can't run on RTLs, as RTLs implementation may support SEW besides the  SEWMIN and LMUL * ELEN range.
>
> We can refer to discussion here: https://github.com/riscv-software-src/riscv-isa-sim/pull/620

I think this is still the right fix, as it seems like it's unlikely
there will be implementations that expect outside that minimum support
to work, see https://github.com/riscv/riscv-isa-manual/issues/2359#issuecomment-3458627615
for example.

>
> In my opinion, we had better add a option such as "frac_sew_check" to make user set right value for their RTL implementation.

In future if there are implementations that want extra support that we
can add a property. Right now I suspect there isn't any software that
expects it to work, so it probably isn't an issue and will help catch
faulty implementations.

Alistair

>
> Otherwise,
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Thanks,
> Zhiwei
>
> We were previously checking VLEN, instead of ELEN, so let's update to
> check ELEN instead of VLEN for fractional scaling.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/vector_helper.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 83dd26314d..b4fc791eb7 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>      target_ulong reserved = s2 &
>                              MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                              xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> -    uint16_t vlen = cpu->cfg.vlenb << 3;
>      int8_t lmul;
>
>      if (vlmul & 4) {
>          /*
>           * Fractional LMUL, check:
>           *
> -         * VLEN * LMUL >= SEW
> -         * VLEN >> (8 - lmul) >= sew
> -         * (vlenb << 3) >> (8 - lmul) >= sew
> +         * ELEN * LMUL >= SEW
> +         * ELEN >> (8 - vlmul) >= sew
>           */
> -        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
> +        if (vlmul == 4 ||
> +            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
>              vill = true;
>          }
>      }

Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check

Posted by LIU Zhiwei 2 days, 12 hours ago

On 4/9/26 1:32 PM, Alistair Francis wrote:
> On Tue, Apr 7, 2026 at 10:13 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>> Hi Alistair,
>>
>> On 4/7/26 12:36 PM, alistair23@gmail.com wrote:
>>
>> From: Alistair Francis <alistair.francis@wdc.com>
>>
>> The RISC-V spec states that
>>
>> """
>> For a given supported fractional LMUL setting, implementations
>> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
>> """
>>
>> I think the meaning  of "must support"  in specification is "must at least support" instead of "must only support".
> Good point, I didn't really think about that.
>
>> Sail or Spike have the same check as this patch to prevent user program can run on them, but
>> can't run on RTLs, as RTLs implementation may support SEW besides the  SEWMIN and LMUL * ELEN range.
>>
>> We can refer to discussion here: https://github.com/riscv-software-src/riscv-isa-sim/pull/620
> I think this is still the right fix, as it seems like it's unlikely
> there will be implementations that expect outside that minimum support
> to work, see https://github.com/riscv/riscv-isa-manual/issues/2359#issuecomment-3458627615
> for example.
Make sense.
>
>> In my opinion, we had better add a option such as "frac_sew_check" to make user set right value for their RTL implementation.
> In future if there are implementations that want extra support that we
> can add a property.
Agree.
> Right now I suspect there isn't any software that
> expects it to work, so it probably isn't an issue and will help catch
> faulty implementations.

Some RTLs can issue more vector instructions one cycle when lmul = 1/2 
than lmul = 1. It is useful for some workloads, such as H264, which 
typical calculation unit is 128 bit.
If vlen is 256bit, software can set lmul to 1/2 (64bit sew is allowed by 
specification, but forbidden by this patch) to issue more vector 
instructions one cycle for this type workload.

Standard software should use this feature by vsetvl and vill detection.  
So it should also work with this patch.

Thanks,
Zhiwei

>
> Alistair
>
>> Otherwise,
>> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>>
>> Thanks,
>> Zhiwei
>>
>> We were previously checking VLEN, instead of ELEN, so let's update to
>> check ELEN instead of VLEN for fractional scaling.
>>
>> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>>   target/riscv/vector_helper.c | 9 ++++-----
>>   1 file changed, 4 insertions(+), 5 deletions(-)
>>
>> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
>> index 83dd26314d..b4fc791eb7 100644
>> --- a/target/riscv/vector_helper.c
>> +++ b/target/riscv/vector_helper.c
>> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>>       target_ulong reserved = s2 &
>>                               MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>>                                               xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>> -    uint16_t vlen = cpu->cfg.vlenb << 3;
>>       int8_t lmul;
>>
>>       if (vlmul & 4) {
>>           /*
>>            * Fractional LMUL, check:
>>            *
>> -         * VLEN * LMUL >= SEW
>> -         * VLEN >> (8 - lmul) >= sew
>> -         * (vlenb << 3) >> (8 - lmul) >= sew
>> +         * ELEN * LMUL >= SEW
>> +         * ELEN >> (8 - vlmul) >= sew
>>            */
>> -        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
>> +        if (vlmul == 4 ||
>> +            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
>>               vill = true;
>>           }
>>       }

Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check

Posted by Daniel Henrique Barboza 4 days, 9 hours ago


On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The RISC-V spec states that
> 
> """
> For a given supported fractional LMUL setting, implementations
> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.
> """
> 
> We were previously checking VLEN, instead of ELEN, so let's update to
> check ELEN instead of VLEN for fractional scaling.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>


>   target/riscv/vector_helper.c | 9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 83dd26314d..b4fc791eb7 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>       target_ulong reserved = s2 &
>                               MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                               xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> -    uint16_t vlen = cpu->cfg.vlenb << 3;
>       int8_t lmul;
>   
>       if (vlmul & 4) {
>           /*
>            * Fractional LMUL, check:
>            *
> -         * VLEN * LMUL >= SEW
> -         * VLEN >> (8 - lmul) >= sew
> -         * (vlenb << 3) >> (8 - lmul) >= sew
> +         * ELEN * LMUL >= SEW
> +         * ELEN >> (8 - vlmul) >= sew
>            */
> -        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
> +        if (vlmul == 4 ||
> +            (cpu->cfg.elen >> (8 - vlmul)) < sew) {
>               vill = true;
>           }
>       }