target/riscv: A collection of bug fixes

[PATCH 4/5] hw/timer: ibex_timer: Update IRQs after writing CTRL

Posted by alistair23@gmail.com 4 days, 14 hours ago

From: Alistair Francis <alistair.francis@wdc.com>

When writing to rv_timer.CTRL after setting the compare values the timer
doesn't fire as we don't update the interrupts. Ensure we update the
interrupts after a write to the rv_timer.CTRL register.

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2796
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/timer/ibex_timer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index 0f12531934..571633803d 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -193,6 +193,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
         break;
     case R_CTRL:
         s->timer_ctrl = val;
+        ibex_timer_update_irqs(s);
         break;
     case R_CFG0:
         qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
-- 
2.53.0

Re: [PATCH 4/5] hw/timer: ibex_timer: Update IRQs after writing CTRL

Posted by Nutty.Liu 2 days, 15 hours ago

On 4/7/2026 12:36 PM, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> When writing to rv_timer.CTRL after setting the compare values the timer
> doesn't fire as we don't update the interrupts. Ensure we update the
> interrupts after a write to the rv_timer.CTRL register.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2796
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
> ---
>   hw/timer/ibex_timer.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index 0f12531934..571633803d 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -193,6 +193,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
>           break;
>       case R_CTRL:
>           s->timer_ctrl = val;
> +        ibex_timer_update_irqs(s);
>           break;
>       case R_CFG0:
>           qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");

Re: [PATCH 4/5] hw/timer: ibex_timer: Update IRQs after writing CTRL

Posted by Chao Liu 3 days, 15 hours ago

On Tue, Apr 07, 2026 at 02:36:13PM +1000, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> When writing to rv_timer.CTRL after setting the compare values the timer
> doesn't fire as we don't update the interrupts. Ensure we update the
> interrupts after a write to the rv_timer.CTRL register.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2796
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao
> ---
>  hw/timer/ibex_timer.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index 0f12531934..571633803d 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -193,6 +193,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
>          break;
>      case R_CTRL:
>          s->timer_ctrl = val;
> +        ibex_timer_update_irqs(s);
>          break;
>      case R_CFG0:
>          qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
> -- 
> 2.53.0
>

Re: [PATCH 4/5] hw/timer: ibex_timer: Update IRQs after writing CTRL

Posted by Philippe Mathieu-Daudé 3 days, 10 hours ago

On 7/4/26 06:36, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> When writing to rv_timer.CTRL after setting the compare values the timer
> doesn't fire as we don't update the interrupts. Ensure we update the
> interrupts after a write to the rv_timer.CTRL register.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2796
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   hw/timer/ibex_timer.c | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 4/5] hw/timer: ibex_timer: Update IRQs after writing CTRL

Posted by Daniel Henrique Barboza 4 days, 8 hours ago


On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> When writing to rv_timer.CTRL after setting the compare values the timer
> doesn't fire as we don't update the interrupts. Ensure we update the
> interrupts after a write to the rv_timer.CTRL register.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2796
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   hw/timer/ibex_timer.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index 0f12531934..571633803d 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -193,6 +193,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
>           break;
>       case R_CTRL:
>           s->timer_ctrl = val;
> +        ibex_timer_update_irqs(s);
>           break;
>       case R_CFG0:
>           qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");

[PATCH 1/5] target/riscv: Generate access fault if sc comparison fails
[PATCH 2/5] linux-user/strace: Add a wrapper for read and write
[PATCH 3/5] target/riscv: Don't OR mip.SEIP when mvien is one
[PATCH 4/5] hw/timer: ibex_timer: Update IRQs after writing CTRL
[PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check