From: Alistair Francis <alistair.francis@wdc.com>

This is a collection of patches to fix a few of the open RISC-V bugs [1].

1: https://gitlab.com/qemu-project/qemu/-/work_items?first_page_size=20&label_name%5B%5D=target%3A%20riscv&sort=created_date&state=opened

Alistair Francis (5):
  target/riscv: Generate access fault if sc comparison fails
  linux-user/strace: Add a wrapper for read and write
  target/riscv: Don't OR mip.SEIP when mvien is one
  hw/timer: ibex_timer: Update IRQs after writing CTRL
  target/riscv: Use ELEN for Fractional LMUL check

 target/riscv/helper.h                   |  3 +++
 hw/timer/ibex_timer.c                   |  1 +
 linux-user/strace.c                     | 14 ++++++++++++++
 target/riscv/csr.c                      |  8 ++++++++
 target/riscv/op_helper.c                | 14 ++++++++++++++
 target/riscv/vector_helper.c            |  9 ++++-----
 target/riscv/insn_trans/trans_rva.c.inc |  6 ++++++
 linux-user/strace.list                  |  4 ++--
 8 files changed, 52 insertions(+), 7 deletions(-)

-- 
2.53.0