On 4/6/26 3:45 PM, Richard Henderson wrote:
> On 4/7/26 04:26, Pierrick Bouvier wrote:
>> We extract aarch64_translate_code function, and stub it accordingly.
>>
>> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> ---
>> target/arm/internals.h | 2 ++
>> target/arm/tcg/stubs32.c | 7 +++++++
>> target/arm/tcg/translate-a64.c | 8 ++++++++
>> target/arm/tcg/translate.c | 19 ++++++++-----------
>> 4 files changed, 25 insertions(+), 11 deletions(-)
>>
>> diff --git a/target/arm/internals.h b/target/arm/internals.h
>> index 8ec27508473..2850edcb198 100644
>> --- a/target/arm/internals.h
>> +++ b/target/arm/internals.h
>> @@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);
>>
>> void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
>> void arm_translate_init(void);
>> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
>> + int *max_insns, vaddr pc, void *host_pc);
>> void arm_translate_code(CPUState *cs, TranslationBlock *tb,
>> int *max_insns, vaddr pc, void *host_pc);
>>
>> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c
>> index c5a0bc61f47..3945dc49e5e 100644
>> --- a/target/arm/tcg/stubs32.c
>> +++ b/target/arm/tcg/stubs32.c
>> @@ -3,6 +3,7 @@
>> */
>>
>> #include "qemu/osdep.h"
>> +#include "target/arm/internals.h"
>> #include "target/arm/tcg/translate.h"
>>
>>
>> @@ -15,3 +16,9 @@ void a64_translate_init(void)
>> {
>> /* Don't initialize for 32 bits. Call site will be fixed later. */
>> }
>> +
>> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
>> + int *max_insns, vaddr pc, void *host_pc)
>> +{
>> + g_assert_not_reached();
>> +}
>> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
>> index ebab9f36f08..db3990576c0 100644
>> --- a/target/arm/tcg/translate-a64.c
>> +++ b/target/arm/tcg/translate-a64.c
>> @@ -10948,3 +10948,11 @@ const TranslatorOps aarch64_translator_ops = {
>> .translate_insn = aarch64_tr_translate_insn,
>> .tb_stop = aarch64_tr_tb_stop,
>> };
>> +
>> +void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,
>> + int *max_insns, vaddr pc, void *host_pc)
>> +{
>> + DisasContext dc = {};
>> + translator_loop(cpu, tb, max_insns, pc, host_pc,
>> + &aarch64_translator_ops, &dc.base, TCG_TYPE_I64);
>> +}
>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
>> index aea38507ef4..9a971325144 100644
>> --- a/target/arm/tcg/translate.c
>> +++ b/target/arm/tcg/translate.c
>> @@ -6906,19 +6906,16 @@ static const TranslatorOps thumb_translator_ops = {
>> void arm_translate_code(CPUState *cpu, TranslationBlock *tb,
>> int *max_insns, vaddr pc, void *host_pc)
>> {
>> - DisasContext dc = { };
>> - const TranslatorOps *ops = &arm_translator_ops;
>> CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);
>> - TCGType addr_type = is_a64(cpu_env(cpu)) ? TCG_TYPE_I64 : TCG_TYPE_I32;
>>
>> - if (EX_TBFLAG_AM32(tb_flags, THUMB)) {
>> - ops = &thumb_translator_ops;
>> - }
>> -#ifdef TARGET_AARCH64
>> if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {
>> - ops = &aarch64_translator_ops;
>> + aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);
>> + } else {
>> + DisasContext dc = { };
>> + translator_loop(cpu, tb, max_insns, pc, host_pc,
>> + (EX_TBFLAG_AM32(tb_flags, THUMB)
>> + ? &thumb_translator_ops
>> + : &arm_translator_ops),
>> + &dc.base, TCG_TYPE_I32);
>> }
>> -#endif
>> -
>> - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, addr_type);
>> }
>
> Oh, I see my confusion on the previous patch.
> Yes, re-ordering this would be helpful.
>
Yes, I think I missed the (implicit idea) that we would have two
different entry points for translations, in two separate files, and thus
TCG_TYPE_VA could automatically set accordingly.
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~