tcg/aarch64/tcg-target.c.inc contains a lot of numbered instruction formats
called "I3XXX" in the enum AArch64Insn, named for the original section in the
Arm documentation which described those formats.

This patch aims to give them more meaningful names, for example, I3314 becomes
Ildstpair. Where possible, these names match those used in
target/arm/tcg/a64.decode.

Changes since the RFC version:
* bitfield_32, logic_imm_32, movw_32 have had the _32 suffix removed since they
  also apply to 64 bit versions here.
* The I3310 mask is now ldst_imm_to_reg; the previous 'to_sign_extend' name was
  wrong.

For convenience, here is a list of the replacements.

* Automatic changes, made by passing the values in the enum to a modified
  version of the code produced by scripts/decodetree.py:
3206 => branch
3305 => ldlit
3306 => stxp
3312 => ldst_imm
3314 => ldstpair
3401 => addsub_imm
3406 => pcrel
3501 => addsub_ext
3502 => addsub_shift
3503 => rrr_sf
3507 => rr_sf
3508 => rrr
3509 => rrrr
3510 => logic_shift
3611 => rrr_e

* Manual changes, still matching names given in a64.decode but found in that
  file manually:
3201 => cbz
3205 => tbz
3207 => bcond_reg
3303 => simd_load_replicate
3403 => extract
3616 => qrrr_e
3617 => qrr_e

* Slightly edited names, from a64.decode but with the '_32' suffix removed,
  since they also apply to 64 bit versions in TCG:
3402 => bitfield
3404 => logic_imm
3405 => movw

* Names invented by me, where a64.decode does not have a meaningful name:
3202 => bcond_imm
3506 => csel
3605 => simd_copy
3606 => simd_imm
3609 => q_shift
3612 => simd_rr
3614 => simd_shift_imm
3502S => addsub_realshift

We've also looked into extracting names from the machine-readable instruction 
descriptions given by Arm. These don't give a 1:1 mapping with many of the
existing names in a64.decode, so would need a much larger restructuring to use.

Thanks to Richard Henderson for initial review on the RFC.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
Jim MacArthur (2):
      tcg/aarch64/tcg-target.c.inc: Replacement of I3XXX names
      tcg/aarch64/tcg-target.c.inc: Manual replace of I3310, I3313

 tcg/aarch64/tcg-target.c.inc | 994 ++++++++++++++++++++++---------------------
 1 file changed, 509 insertions(+), 485 deletions(-)
---
base-commit: 7df28e4c41c45a68afbc60766c2111358fc7fd37
change-id: 20260402-aarch64-tcg-instruction-format-rename2-2268117e6158

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>

On 4/3/26 00:20, Jim MacArthur wrote:
> tcg/aarch64/tcg-target.c.inc contains a lot of numbered instruction formats
> called "I3XXX" in the enum AArch64Insn, named for the original section in the
> Arm documentation which described those formats.
> 
> This patch aims to give them more meaningful names, for example, I3314 becomes
> Ildstpair. Where possible, these names match those used in
> target/arm/tcg/a64.decode.
> 
> Changes since the RFC version:
> * bitfield_32, logic_imm_32, movw_32 have had the _32 suffix removed since they
>    also apply to 64 bit versions here.
> * The I3310 mask is now ldst_imm_to_reg; the previous 'to_sign_extend' name was
>    wrong.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

I'll queue this to tcg-next for 11.1.

r~