From: Yodel Eldar <yodel.eldar@yodel.dev>

Hi,

This series is intended as a leg of a re-spin of the
"QOMify Clipper and Typhoon" series [1]. There, thanks to
a suggestion by Philippe, we decided to decouple the Alpha
CPU from the Typhoon chipset to improve the machine model.

Currently, the CPU owns a QEMUTimer and its state owns the
alarm expiration of that alarm timer. Modification of the
timer is triggered via a QEMU-specific synthetic processor
register in PALcode by changing the expiration value through
the side effect invocation of a TCG helper function,
helper_set_alarm(). Meanwhile, the timer alarm callback is
defined in the Typhoon chipset, so the creation of the timer
occurs during the realization of the chipset; thus, the
typhoon must have access to CPU internals in violation of
encapsulation and architectural accuracy. Instead, as
Philippe pointed out, the chipset should just communicate
with the CPU through an IRQ line wired by the board.

This series does that by removing the timer out of the CPU
and into the chipset. The alarm expiration now resides in
an QEMU-specific (non-standard) Cchip MMIO register at
offset 0x7c0 as implemented in the PALcode binary. The
logic as to what happens when alarm expiration is modified
remains the same as before, but now we don't need the TCG
helper function or the magic process register that triggers
its invocation.

I'm submitting this series primarily to get feedback on
the third and fourth patches, because it blurs the line
of a refactor and a functional change; moreover, it
necessitates a change in an external dependency
(qemu-palcode), so I'm particularly interested in Richard's
(its owner) opinion on the shift from a synthetic processor
register to a vendor-specific MMIO register.

If we agree to take this route, as mentioned earlier, this
series will be folded into the QOMification series that
motivated it.

Patch 4 contains the modified palcode-clipper binary so
that testers would not need to build it themselves, but
my intent is to submit a PR to the qemu-palcode repo. The
diff of the source changes to palcode-clipper are in the
notes of Patch 4.

Patch 3 depends on Patch 4, so they'd need to be squashed
together to avoid breaking bisect.

Patch 2 is much more straightforward: the Typhoon needs
access to the CPU index for its read of the Cchip's MISC
register; right now, we use current_cpu to get the index,
but this is an antipattern, because it violates
encapsulation. Instead, we designate the requester_id
attribute in MemTxAttrs for the CPU index.

Patch 1 defines the instance_init for the Typhoon, so that
we can instantiate the Typhoon in clipper_init() and
connect the IRQ lines between the CPU and Typhoon there in
Patch 3.

I look forward to your feedback.

Thanks,
Yodel

[1] https://lore.kernel.org/qemu-devel/20260310-qomify-alpha-v1-0-4375b00a85ff@yodel.dev/

Yodel Eldar (4):
  alpha: Define Typhoon instance_init
  alpha: Propagate CPU index via MemTxAttrs
  alpha: Replace helper_set_alarm with Typhoon Cchip MMIO register
  pc-bios/palcode-clipper: Replace qemu_alarm with Cchip register

 hw/alpha/alpha_sys.h      |   4 ++-
 hw/alpha/dp264.c          |  12 ++++++-
 hw/alpha/typhoon.c        |  69 ++++++++++++++++++++++++++------------
 pc-bios/palcode-clipper   | Bin 153728 -> 154432 bytes
 target/alpha/cpu.c        |  17 ++++++++++
 target/alpha/cpu.h        |   6 ----
 target/alpha/helper.c     |  15 +++++++--
 target/alpha/helper.h     |   1 -
 target/alpha/sys_helper.c |  12 -------
 target/alpha/translate.c  |  11 ------
 10 files changed, 91 insertions(+), 56 deletions(-)

-- 
2.53.0