This new header defines a new type for target virtual address,
independent from TCGv and is parameterized by a new define
TCG_ADDRESS_BITS (name was suggested by Paolo instead of
TARGET_ADDRESS_BITS).
By default, tcg-op.h include set this define to TARGET_LONG_BITS, but
it's also possible to include only tcg-op-common.h and tcg-op-mem.h and
set TCG_ADDRESS_BITS manually, which is what next commits will do.
We preserve existing MIT license when extracting this new header.
Implemented from:
https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++
include/tcg/tcg-op.h | 100 +------------------------------
2 files changed, 129 insertions(+), 97 deletions(-)
create mode 100644 include/tcg/tcg-op-mem.h
diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h
new file mode 100644
index 00000000000..36931d1dd57
--- /dev/null
+++ b/include/tcg/tcg-op-mem.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Target dependent memory related functions.
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ */
+
+#ifndef TCG_TCG_OP_MEM_H
+#define TCG_TCG_OP_MEM_H
+
+#ifndef TCG_ADDRESS_BITS
+#error TCG_ADDRESS_BITS must be defined
+#endif
+
+#if TCG_ADDRESS_BITS == 32
+typedef TCGv_i32 TCGv_va;
+#define TCG_TYPE_VA TCG_TYPE_I32
+#define tcgv_va_temp tcgv_i32_temp
+#define tcgv_va_temp_new tcg_temp_new_i32
+#elif TCG_ADDRESS_BITS == 64
+typedef TCGv_i64 TCGv_va;
+#define TCG_TYPE_VA TCG_TYPE_I64
+#define tcgv_va_temp tcgv_i64_temp
+#define tcgv_va_temp_new tcg_temp_new_i64
+#else
+#error
+#endif
+
+static inline void
+tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m)
+{
+ tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
+}
+
+static inline void
+tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m)
+{
+ tcg_gen_qemu_st_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
+}
+
+static inline void
+tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m)
+{
+ tcg_gen_qemu_ld_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
+}
+
+static inline void
+tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m)
+{
+ tcg_gen_qemu_st_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
+}
+
+static inline void
+tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m)
+{
+ tcg_gen_qemu_ld_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
+}
+
+static inline void
+tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m)
+{
+ tcg_gen_qemu_st_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
+}
+
+#define DEF_ATOMIC2(N, S) \
+ static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, \
+ TCGArg i, MemOp m) \
+ { N##_##S##_chk(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); }
+
+#define DEF_ATOMIC3(N, S) \
+ static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, \
+ TCGv_##S n, TCGArg i, MemOp m) \
+ { N##_##S##_chk(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); }
+
+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32)
+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64)
+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128)
+
+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32)
+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64)
+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128)
+
+DEF_ATOMIC2(tcg_gen_atomic_xchg, i32)
+DEF_ATOMIC2(tcg_gen_atomic_xchg, i64)
+DEF_ATOMIC2(tcg_gen_atomic_xchg, i128)
+
+DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32)
+DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64)
+
+DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64)
+DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32)
+DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
+
+#undef DEF_ATOMIC2
+#undef DEF_ATOMIC3
+
+#endif /* TCG_TCG_OP_MEM_H */
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 7024be938e6..96a5af1a298 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -16,6 +16,9 @@
#error must include QEMU headers
#endif
+#define TCG_ADDRESS_BITS TARGET_LONG_BITS
+#include "tcg/tcg-op-mem.h"
+
#if TARGET_LONG_BITS == 32
# define TCG_TYPE_TL TCG_TYPE_I32
#elif TARGET_LONG_BITS == 64
@@ -46,103 +49,6 @@ typedef TCGv_i64 TCGv;
#error Unhandled TARGET_LONG_BITS value
#endif
-static inline void
-tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m)
-{
- tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
-}
-
-static inline void
-tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m)
-{
- tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
-}
-
-static inline void
-tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m)
-{
- tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
-}
-
-static inline void
-tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m)
-{
- tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
-}
-
-static inline void
-tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m)
-{
- tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
-}
-
-static inline void
-tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m)
-{
- tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
-}
-
-#define DEF_ATOMIC2(N, S) \
- static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \
- TCGArg i, MemOp m) \
- { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); }
-
-#define DEF_ATOMIC3(N, S) \
- static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \
- TCGv_##S n, TCGArg i, MemOp m) \
- { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); }
-
-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32)
-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64)
-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128)
-
-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32)
-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64)
-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128)
-
-DEF_ATOMIC2(tcg_gen_atomic_xchg, i32)
-DEF_ATOMIC2(tcg_gen_atomic_xchg, i64)
-DEF_ATOMIC2(tcg_gen_atomic_xchg, i128)
-
-DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32)
-DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64)
-
-DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64)
-DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32)
-DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
-
-#undef DEF_ATOMIC2
-#undef DEF_ATOMIC3
-
#if TARGET_LONG_BITS == 64
#define tcg_gen_movi_tl tcg_gen_movi_i64
#define tcg_gen_mov_tl tcg_gen_mov_i64
--
2.47.3On 27/3/26 17:50, Pierrick Bouvier wrote: > This new header defines a new type for target virtual address, > independent from TCGv and is parameterized by a new define > TCG_ADDRESS_BITS (name was suggested by Paolo instead of > TARGET_ADDRESS_BITS). > > By default, tcg-op.h include set this define to TARGET_LONG_BITS, but > it's also possible to include only tcg-op-common.h and tcg-op-mem.h and > set TCG_ADDRESS_BITS manually, which is what next commits will do. > > We preserve existing MIT license when extracting this new header. > > Implemented from: > https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ > > Suggested-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++ > include/tcg/tcg-op.h | 100 +------------------------------ > 2 files changed, 129 insertions(+), 97 deletions(-) > create mode 100644 include/tcg/tcg-op-mem.h > > diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h > new file mode 100644 > index 00000000000..36931d1dd57 > --- /dev/null > +++ b/include/tcg/tcg-op-mem.h > @@ -0,0 +1,126 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Target dependent memory related functions. > + * > + * Copyright (c) 2008 Fabrice Bellard > + */ > + > +#ifndef TCG_TCG_OP_MEM_H > +#define TCG_TCG_OP_MEM_H > + > +#ifndef TCG_ADDRESS_BITS > +#error TCG_ADDRESS_BITS must be defined Alternatively rename as tcg-op-mem.h.inc and check for TCG_TCG_OP_H, erroring "this header can't be included directly" or "can only be included by "tcg/tcg-op.h"? > +#endif > + > +#if TCG_ADDRESS_BITS == 32 > +typedef TCGv_i32 TCGv_va; > +#define TCG_TYPE_VA TCG_TYPE_I32 > +#define tcgv_va_temp tcgv_i32_temp > +#define tcgv_va_temp_new tcg_temp_new_i32 > +#elif TCG_ADDRESS_BITS == 64 > +typedef TCGv_i64 TCGv_va; > +#define TCG_TYPE_VA TCG_TYPE_I64 > +#define tcgv_va_temp tcgv_i64_temp > +#define tcgv_va_temp_new tcg_temp_new_i64 > +#else > +#error > +#endif > + ... > + > +#endif /* TCG_TCG_OP_MEM_H */ > diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h > index 7024be938e6..96a5af1a298 100644 > --- a/include/tcg/tcg-op.h > +++ b/include/tcg/tcg-op.h > @@ -16,6 +16,9 @@ > #error must include QEMU headers > #endif > > +#define TCG_ADDRESS_BITS TARGET_LONG_BITS > +#include "tcg/tcg-op-mem.h" > + > #if TARGET_LONG_BITS == 32 > # define TCG_TYPE_TL TCG_TYPE_I32 > #elif TARGET_LONG_BITS == 64 > @@ -46,103 +49,6 @@ typedef TCGv_i64 TCGv; > #error Unhandled TARGET_LONG_BITS value > #endif ...
On 1/4/26 14:13, Philippe Mathieu-Daudé wrote: > On 27/3/26 17:50, Pierrick Bouvier wrote: >> This new header defines a new type for target virtual address, >> independent from TCGv and is parameterized by a new define >> TCG_ADDRESS_BITS (name was suggested by Paolo instead of >> TARGET_ADDRESS_BITS). >> >> By default, tcg-op.h include set this define to TARGET_LONG_BITS, but >> it's also possible to include only tcg-op-common.h and tcg-op-mem.h and >> set TCG_ADDRESS_BITS manually, which is what next commits will do. >> >> We preserve existing MIT license when extracting this new header. >> >> Implemented from: >> https://lore.kernel.org/qemu-devel/ >> a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ >> >> Suggested-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++ >> include/tcg/tcg-op.h | 100 +------------------------------ >> 2 files changed, 129 insertions(+), 97 deletions(-) >> create mode 100644 include/tcg/tcg-op-mem.h >> >> diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h >> new file mode 100644 >> index 00000000000..36931d1dd57 >> --- /dev/null >> +++ b/include/tcg/tcg-op-mem.h >> @@ -0,0 +1,126 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Target dependent memory related functions. >> + * >> + * Copyright (c) 2008 Fabrice Bellard >> + */ >> + >> +#ifndef TCG_TCG_OP_MEM_H >> +#define TCG_TCG_OP_MEM_H >> + >> +#ifndef TCG_ADDRESS_BITS >> +#error TCG_ADDRESS_BITS must be defined > > Alternatively rename as tcg-op-mem.h.inc and check for TCG_TCG_OP_H, > erroring "this header can't be included directly" or "can only be > included by "tcg/tcg-op.h"? Complementing my thougth, in "tcg/tcg-op-mem32.h": #define TCG_ADDRESS_BITS 32 #include "tcg/tcg-op-mem.h.inc" and similar in "tcg/tcg-op-mem64.h" (or "tcg/tcg-op64-mem.h"). > >> +#endif >> + >> +#if TCG_ADDRESS_BITS == 32 >> +typedef TCGv_i32 TCGv_va; >> +#define TCG_TYPE_VA TCG_TYPE_I32 >> +#define tcgv_va_temp tcgv_i32_temp >> +#define tcgv_va_temp_new tcg_temp_new_i32 >> +#elif TCG_ADDRESS_BITS == 64 >> +typedef TCGv_i64 TCGv_va; >> +#define TCG_TYPE_VA TCG_TYPE_I64 >> +#define tcgv_va_temp tcgv_i64_temp >> +#define tcgv_va_temp_new tcg_temp_new_i64 >> +#else >> +#error >> +#endif >> + > > ... > >> + >> +#endif /* TCG_TCG_OP_MEM_H */ >> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h >> index 7024be938e6..96a5af1a298 100644 >> --- a/include/tcg/tcg-op.h >> +++ b/include/tcg/tcg-op.h >> @@ -16,6 +16,9 @@ >> #error must include QEMU headers >> #endif >> +#define TCG_ADDRESS_BITS TARGET_LONG_BITS >> +#include "tcg/tcg-op-mem.h" >> + >> #if TARGET_LONG_BITS == 32 >> # define TCG_TYPE_TL TCG_TYPE_I32 >> #elif TARGET_LONG_BITS == 64 >> @@ -46,103 +49,6 @@ typedef TCGv_i64 TCGv; >> #error Unhandled TARGET_LONG_BITS value >> #endif > > ...
On 4/1/26 5:13 AM, Philippe Mathieu-Daudé wrote: > On 27/3/26 17:50, Pierrick Bouvier wrote: >> This new header defines a new type for target virtual address, >> independent from TCGv and is parameterized by a new define >> TCG_ADDRESS_BITS (name was suggested by Paolo instead of >> TARGET_ADDRESS_BITS). >> >> By default, tcg-op.h include set this define to TARGET_LONG_BITS, but >> it's also possible to include only tcg-op-common.h and tcg-op-mem.h and >> set TCG_ADDRESS_BITS manually, which is what next commits will do. >> >> We preserve existing MIT license when extracting this new header. >> >> Implemented from: >> https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ >> >> Suggested-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++ >> include/tcg/tcg-op.h | 100 +------------------------------ >> 2 files changed, 129 insertions(+), 97 deletions(-) >> create mode 100644 include/tcg/tcg-op-mem.h >> >> diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h >> new file mode 100644 >> index 00000000000..36931d1dd57 >> --- /dev/null >> +++ b/include/tcg/tcg-op-mem.h >> @@ -0,0 +1,126 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Target dependent memory related functions. >> + * >> + * Copyright (c) 2008 Fabrice Bellard >> + */ >> + >> +#ifndef TCG_TCG_OP_MEM_H >> +#define TCG_TCG_OP_MEM_H >> + >> +#ifndef TCG_ADDRESS_BITS >> +#error TCG_ADDRESS_BITS must be defined > > Alternatively rename as tcg-op-mem.h.inc and check for TCG_TCG_OP_H, > erroring "this header can't be included directly" or "can only be > included by "tcg/tcg-op.h"? > The idea is that it can be either included from "tcg/tcg-op.h" for target specific code, and directly in common code, by manually setting TCG_ADDRESS_BITS accordingly. >> +#endif >> + >> +#if TCG_ADDRESS_BITS == 32 >> +typedef TCGv_i32 TCGv_va; >> +#define TCG_TYPE_VA TCG_TYPE_I32 >> +#define tcgv_va_temp tcgv_i32_temp >> +#define tcgv_va_temp_new tcg_temp_new_i32 >> +#elif TCG_ADDRESS_BITS == 64 >> +typedef TCGv_i64 TCGv_va; >> +#define TCG_TYPE_VA TCG_TYPE_I64 >> +#define tcgv_va_temp tcgv_i64_temp >> +#define tcgv_va_temp_new tcg_temp_new_i64 >> +#else >> +#error >> +#endif >> + > > ... > >> + >> +#endif /* TCG_TCG_OP_MEM_H */ >> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h >> index 7024be938e6..96a5af1a298 100644 >> --- a/include/tcg/tcg-op.h >> +++ b/include/tcg/tcg-op.h >> @@ -16,6 +16,9 @@ >> #error must include QEMU headers >> #endif >> >> +#define TCG_ADDRESS_BITS TARGET_LONG_BITS >> +#include "tcg/tcg-op-mem.h" >> + >> #if TARGET_LONG_BITS == 32 >> # define TCG_TYPE_TL TCG_TYPE_I32 >> #elif TARGET_LONG_BITS == 64 >> @@ -46,103 +49,6 @@ typedef TCGv_i64 TCGv; >> #error Unhandled TARGET_LONG_BITS value >> #endif > > ...
On 3/28/26 02:50, Pierrick Bouvier wrote: > This new header defines a new type for target virtual address, > independent from TCGv and is parameterized by a new define > TCG_ADDRESS_BITS (name was suggested by Paolo instead of > TARGET_ADDRESS_BITS). > > By default, tcg-op.h include set this define to TARGET_LONG_BITS, but > it's also possible to include only tcg-op-common.h and tcg-op-mem.h and > set TCG_ADDRESS_BITS manually, which is what next commits will do. > > We preserve existing MIT license when extracting this new header. > > Implemented from: > https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ > > Suggested-by: Richard Henderson<richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++ > include/tcg/tcg-op.h | 100 +------------------------------ > 2 files changed, 129 insertions(+), 97 deletions(-) > create mode 100644 include/tcg/tcg-op-mem.h Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 27/3/26 17:50, Pierrick Bouvier wrote: > This new header defines a new type for target virtual address, > independent from TCGv and is parameterized by a new define > TCG_ADDRESS_BITS (name was suggested by Paolo instead of > TARGET_ADDRESS_BITS). > > By default, tcg-op.h include set this define to TARGET_LONG_BITS, but > it's also possible to include only tcg-op-common.h and tcg-op-mem.h and > set TCG_ADDRESS_BITS manually, which is what next commits will do. > > We preserve existing MIT license when extracting this new header. > > Implemented from: > https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ > > Suggested-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++ > include/tcg/tcg-op.h | 100 +------------------------------ > 2 files changed, 129 insertions(+), 97 deletions(-) > create mode 100644 include/tcg/tcg-op-mem.h Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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