On 3/27/26 10:30 AM, Philippe Mathieu-Daudé wrote:
> On 27/3/26 17:50, Pierrick Bouvier wrote:
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> ---
>> target/arm/tcg/translate.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
>> index 4546bbeeeff..204f9657993 100644
>> --- a/target/arm/tcg/translate.c
>> +++ b/target/arm/tcg/translate.c
>> @@ -6450,7 +6450,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
>> * fields here.
>> */
>> uint32_t condexec_bits;
>> - target_ulong pc_arg = dc->base.pc_next;
>> + uint32_t pc_arg = dc->base.pc_next;
>>
>> if (tb_cflags(dcbase->tb) & CF_PCREL) {
>> pc_arg &= ~TARGET_PAGE_MASK;
>> @@ -6612,7 +6612,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>> bool is_16bit;
>> /* TCG op to rewind to if this turns out to be an invalid ECI state */
>> TCGOp *insn_eci_rewind = NULL;
>> - target_ulong insn_eci_pc_save = -1;
>> + uint32_t insn_eci_pc_save = -1;
>>
>> /* Misaligned thumb PC is architecturally impossible. */
>> assert((dc->base.pc_next & 1) == 0);
>
> I'd have expected vaddr, but uint32_t is correct enough.
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
While it works, semantically, in this case, we know this addr is 32-bit
only, even when compiling for aarch64-softmmu target.