[PATCH v2 04/65] hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board

When building the Arm "virt" board, pull in the GICv5.

We haven't added support for creating or wiring up the GICv5 in that
board yet, but adding it to the Kconfig early means that the GICv5
code will be compiled and so we can have more confidence that the
individual commits building it up are correct (or at least compile).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
 hw/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4e50fb1111..e1a6dba1e9 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -10,6 +10,7 @@ config ARM_VIRT
     imply NVDIMM
     imply IOMMUFD
     select ARM_GIC
+    select ARM_GICV5
     select ACPI
     select ARM_SMMUV3
     select GPIO_KEY
-- 
2.43.0

• [PATCH v2 01/65] qom/object: Add object_resolve_and_typecheck()
• [PATCH v2 02/65] hw/core: Permit devices to define an array of link properties
• [PATCH v2 03/65] hw/intc: Skeleton of GICv5 IRS classes
• [PATCH v2 04/65] hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board
• [PATCH v2 05/65] hw/intc/arm_gicv5: Implement skeleton code for IRS register frames
• [PATCH v2 06/65] hw/intc/arm_gicv5: Add migration blocker
• [PATCH v2 07/65] hw/intc/arm_gicv5: Create and validate QOM properties
• [PATCH v2 08/65] hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs
• [PATCH v2 09/65] hw/intc/arm_gicv5: Define macros for config frame registers
• [PATCH v2 10/65] hw/intc/arm_gicv5: Implement IRS ID regs
• [PATCH v2 11/65] hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA
• [PATCH v2 12/65] hw/intc/arm_gicv5: Implement gicv5_class_name()
• [PATCH v2 13/65] hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs
• [PATCH v2 14/65] target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns
• [PATCH v2 15/65] target/arm: Set up pointer to GICv5 in each CPU
• [PATCH v2 16/65] hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR}
• [PATCH v2 17/65] hw/intc/arm_gicv5: Cache LPI IST config in a struct
• [PATCH v2 18/65] hw/intc/arm_gicv5: Implement gicv5_set_priority()
• [PATCH v2 19/65] target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction
• [PATCH v2 20/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR
• [PATCH v2 21/65] hw/intc/arm_gicv5: Implement remaining set-config functions
• [PATCH v2 22/65] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config
• [PATCH v2 23/65] hw/intc/arm_gicv5: Create backing state for SPIs
• [PATCH v2 24/65] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state
• [PATCH v2 25/65] hw/intc/arm_gicv5: Implement gicv5_request_config()
• [PATCH v2 26/65] target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1
• [PATCH v2 27/65] hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR}
• [PATCH v2 28/65] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events
• [PATCH v2 29/65] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1
• [PATCH v2 30/65] hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR
• [PATCH v2 31/65] hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR}
• [PATCH v2 32/65] hw/intc/arm_gicv5: Implement CoreSight ID registers
• [PATCH v2 33/65] hw/intc/arm_gicv5: Cache pending LPIs in a hash table
• [PATCH v2 34/65] target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1
• [PATCH v2 35/65] target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1
• [PATCH v2 36/65] target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear registers
• [PATCH v2 37/65] target/arm: GICv5 cpuif: Implement PPI handling mode register
• [PATCH v2 38/65] target/arm: GICv5 cpuif: Implement PPI pending status registers
• [PATCH v2 39/65] target/arm: GICv5 cpuif: Implement PPI enable register
• [PATCH v2 40/65] target/arm: GICv5 cpuif: Implement PPI priority registers
• [PATCH v2 41/65] target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1
• [PATCH v2 42/65] target/arm: GICv5 cpuif: Calculate the highest priority PPI
• [PATCH v2 43/65] hw/intc/arm_gicv5: Calculate HPPI in the IRS
• [PATCH v2 44/65] target/arm: GICv5 cpuif: Implement ICC_CR0_EL1
• [PATCH v2 45/65] target/arm: GICv5 cpuif: Implement ICC_PCR_EL1
• [PATCH v2 46/65] target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1
• [PATCH v2 47/65] hw/intc/arm_gicv5: Implement Activate command
• [PATCH v2 48/65] target/arm: GICv5 cpuif: Implement GICR CDIA command
• [PATCH v2 49/65] target/arm: GICv5 cpuif: Implement GIC CDEOI
• [PATCH v2 50/65] hw/intc/arm_gicv5: Implement Deactivate command
• [PATCH v2 51/65] target/arm: GICv5 cpuif: Implement GIC CDDI
• [PATCH v2 52/65] target/arm: GICv5 cpuif: Signal IRQ or FIQ
• [PATCH v2 53/65] target/arm: Connect internal interrupt sources up as GICv5 PPIs
• [PATCH v2 54/65] target/arm: Add has_gcie property to enable FEAT_GCIE
• [PATCH v2 55/65] hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif
• [PATCH v2 56/65] hw/arm/virt: Remember CPU phandles rather than looking them up by name
• [PATCH v2 57/65] hw/arm/virt: Move MSI controller creation out of create_gic()
• [PATCH v2 58/65] hw/arm/virt: Pull "wire CPU interrupts" out of create_gic()
• [PATCH v2 59/65] hw/arm/virt: Split GICv2 and GICv3/4 creation
• [PATCH v2 60/65] hw/arm/virt: Create and connect GICv5
• [PATCH v2 61/65] hw/arm/virt: Advertise GICv5 in the DTB
• [PATCH v2 62/65] hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs
• [PATCH v2 63/65] hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB
• [PATCH v2 64/65] hw/arm/virt: Enable GICv5 CPU interface when using GICv5
• [PATCH v2 65/65] hw/arm/virt: Allow user to select GICv5