The IRS has multiple ISTs, for different contexts:
* physical LPIs (separately for each interrupt domain)
* virtual LPIs
* virtual SPIs
The config information for physical LPIs is in the IRS_IST_BASER and
IRS_IST_CFGR registers; for virtual LPIs and virtual SPIs it will be
in the L2_VMTE VM table entry. We would like to be able to write
generic code that can manipulate any of these ISTs. Define a struct
which captures the config information for an IST, and cache the
IRS_IST_CFGR/IRS_IST_BASER data into this format when the guest sets
the VALID bit.
This also allows us to enforce the correct handling of reserved and
out-of-range values, and expand the encodings of sizes into a more
convenient format for later use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
hw/intc/arm_gicv5.c | 64 +++++++++++++++++++++++++++++++++++++
hw/intc/trace-events | 2 ++
include/hw/intc/arm_gicv5.h | 12 +++++++
3 files changed, 78 insertions(+)
diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
index cbb35c0270..172c5be0d4 100644
--- a/hw/intc/arm_gicv5.c
+++ b/hw/intc/arm_gicv5.c
@@ -278,9 +278,68 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)
}
cs->irs_ist_baser[domain] = FIELD_DP64(cs->irs_ist_baser[domain],
IRS_IST_BASER, VALID, valid);
+ s->phys_lpi_config[domain].valid = false;
+ trace_gicv5_ist_invalid(domain_name[domain]);
return;
}
cs->irs_ist_baser[domain] = value;
+
+ if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {
+ /*
+ * If the guest just set VALID then capture data into config struct,
+ * sanitize the reserved values, and expand fields out into byte counts.
+ */
+ GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];
+ uint8_t istbits, l2bits, l2_idx_bits;
+ uint8_t id_bits = FIELD_EX64(cs->irs_ist_cfgr[domain],
+ IRS_IST_CFGR, LPI_ID_BITS);
+ id_bits = MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GICV5_ID_BITS);
+
+ switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, ISTSZ)) {
+ case 0:
+ case 3: /* reserved: acts like the minimum required size */
+ istbits = 2;
+ break;
+ case 1:
+ istbits = 3;
+ break;
+ case 2:
+ istbits = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, L2SZ)) {
+ case 0:
+ case 3: /* reserved; CONSTRAINED UNPREDICTABLE */
+ l2bits = 12; /* 4K: 12 bits */
+ break;
+ case 1:
+ l2bits = 14; /* 16K: 14 bits */
+ break;
+ case 2:
+ l2bits = 16; /* 64K: 16 bits */
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ /*
+ * Calculate how many bits of an ID index the L2 table
+ * (e.g. if we need 14 bits to index each byte in a 16K L2 table,
+ * but each entry is 4 bytes wide then we need 14 - 2 = 12 bits
+ * to index an entry in the table).
+ */
+ l2_idx_bits = l2bits - istbits;
+ cfg->base = cs->irs_ist_baser[domain] & R_IRS_IST_BASER_ADDR_MASK;
+ cfg->id_bits = id_bits;
+ cfg->istsz = 1 << istbits;
+ cfg->l2_idx_bits = l2_idx_bits;
+ cfg->structure = FIELD_EX64(cs->irs_ist_cfgr[domain],
+ IRS_IST_CFGR, STRUCTURE);
+ cfg->valid = true;
+ trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits,
+ cfg->l2_idx_bits, cfg->istsz, cfg->structure);
+ }
}
static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
@@ -553,6 +612,11 @@ static void gicv5_reset_hold(Object *obj, ResetType type)
if (c->parent_phases.hold) {
c->parent_phases.hold(obj, type);
}
+
+ /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */
+ for (int i = 0; i < NUM_GICV5_DOMAINS; i++) {
+ s->phys_lpi_config[i].valid = false;
+ }
}
static void gicv5_set_idregs(GICv5Common *cs)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 0797a23c1a..80fc47794b 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -233,6 +233,8 @@ gicv5_badread(const char *domain, uint64_t offset, unsigned size) "GICv5 IRS %s
gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigned size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error"
gicv5_spi(uint32_t id, int level) "GICv5 SPI ID %u asserted at level %d"
+gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_t l2_idx_bits, uint8_t istsz, bool structure) "GICv5 IRS %s IST now valid: base 0x%" PRIx64 " id_bits %u l2_idx_bits %u IST entry size %u 2-level %d"
+gicv5_ist_invalid(const char *domain) "GICv5 IRS %s IST no longer valid"
# arm_gicv5_common.c
gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u"
diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h
index 42ccef8474..f6ecd9c323 100644
--- a/include/hw/intc/arm_gicv5.h
+++ b/include/hw/intc/arm_gicv5.h
@@ -17,11 +17,23 @@
OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5)
+typedef struct GICv5ISTConfig {
+ hwaddr base; /* Base address */
+ uint8_t id_bits; /* number of bits in an ID for this table */
+ uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */
+ uint8_t istsz; /* L2 ISTE size in bytes */
+ bool structure; /* true if using 2-level table */
+ bool valid; /* true if this table is valid and usable */
+} GICv5ISTConfig;
+
/*
* This class is for TCG-specific state for the GICv5.
*/
struct GICv5 {
GICv5Common parent_obj;
+
+ /* This is the info from IRS_IST_BASER and IRS_IST_CFGR */
+ GICv5ISTConfig phys_lpi_config[NUM_GICV5_DOMAINS];
};
struct GICv5Class {
--
2.43.0