Implement the .virtio_is_big_endian SysemuCPUOps callback for RISC-V.
This makes cpu_virtio_is_big_endian() return the correct endianness
based on the hart's MSTATUS MBE/SBE/UBE bits, which is used by
virtio_current_cpu_endian() during guest-initiated device resets.

For bi-endian RISC-V targets, this ensures legacy virtio devices
correctly detect the guest's runtime data endianness, matching
how ARM handles its bi-endian support.

Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
 target/riscv/cpu.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eed5afd27e..f813acf579 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -32,6 +32,7 @@
 #include "migration/vmstate.h"
 #include "fpu/softfloat-helpers.h"
 #include "system/device_tree.h"
+#include "system/hw_accel.h"
 #include "system/kvm.h"
 #include "system/tcg.h"
 #include "kvm/kvm_riscv.h"
@@ -2713,11 +2714,21 @@ static int64_t riscv_get_arch_id(CPUState *cs)
 
 #include "hw/core/sysemu-cpu-ops.h"
 
+static bool riscv_cpu_virtio_is_big_endian(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    cpu_synchronize_state(cs);
+    return riscv_cpu_data_is_big_endian(env);
+}
+
 static const struct SysemuCPUOps riscv_sysemu_ops = {
     .has_work = riscv_cpu_has_work,
     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
     .write_elf64_note = riscv_cpu_write_elf64_note,
     .write_elf32_note = riscv_cpu_write_elf32_note,
+    .internal_is_big_endian = riscv_cpu_virtio_is_big_endian,
     .legacy_vmsd = &vmstate_riscv_cpu,
 };
 #endif
-- 
2.34.1

On 3/25/26 02:40, Djordje Todorovic wrote:
> Implement the .virtio_is_big_endian SysemuCPUOps callback for RISC-V.
> This makes cpu_virtio_is_big_endian() return the correct endianness
> based on the hart's MSTATUS MBE/SBE/UBE bits, which is used by
> virtio_current_cpu_endian() during guest-initiated device resets.
> 
> For bi-endian RISC-V targets, this ensures legacy virtio devices
> correctly detect the guest's runtime data endianness, matching
> how ARM handles its bi-endian support.
> 
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
>   target/riscv/cpu.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)

Nack.

I replied to v4 before I saw v5:
https://lore.kernel.org/qemu-devel/23a0d240-6f77-4edb-8128-fd2c2b8354df@linaro.org/


r~

> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eed5afd27e..f813acf579 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -32,6 +32,7 @@
>   #include "migration/vmstate.h"
>   #include "fpu/softfloat-helpers.h"
>   #include "system/device_tree.h"
> +#include "system/hw_accel.h"
>   #include "system/kvm.h"
>   #include "system/tcg.h"
>   #include "kvm/kvm_riscv.h"
> @@ -2713,11 +2714,21 @@ static int64_t riscv_get_arch_id(CPUState *cs)
>   
>   #include "hw/core/sysemu-cpu-ops.h"
>   
> +static bool riscv_cpu_virtio_is_big_endian(CPUState *cs)
> +{
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +    CPURISCVState *env = &cpu->env;
> +
> +    cpu_synchronize_state(cs);
> +    return riscv_cpu_data_is_big_endian(env);
> +}
> +
>   static const struct SysemuCPUOps riscv_sysemu_ops = {
>       .has_work = riscv_cpu_has_work,
>       .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
>       .write_elf64_note = riscv_cpu_write_elf64_note,
>       .write_elf32_note = riscv_cpu_write_elf32_note,
> +    .internal_is_big_endian = riscv_cpu_virtio_is_big_endian,
>       .legacy_vmsd = &vmstate_riscv_cpu,
>   };
>   #endif