Adding functional test case for riscv big-endian.

Djordje Todorovic (7):
  target/riscv: Add big-endian CPU property
  target/riscv: Set endianness MSTATUS bits at CPU reset
  target/riscv: Implement runtime data endianness via MSTATUS bits
  hw/riscv: Make boot code endianness-aware at runtime
  target/riscv: Fix page table walk endianness for big-endian harts
  target/riscv: Support runtime endianness in virtio via sysemu callback
  target/riscv: Add test for RISC-V BE

 hw/riscv/boot.c                            | 82 ++++++++++++++++++----
 include/hw/riscv/boot.h                    |  2 +
 target/riscv/cpu.c                         | 22 ++++--
 target/riscv/cpu.h                         | 28 ++++++++
 target/riscv/cpu_cfg_fields.h.inc          |  1 +
 target/riscv/cpu_helper.c                  | 28 ++++++--
 target/riscv/internals.h                   |  9 +--
 target/riscv/tcg/tcg-cpu.c                 |  9 ++-
 target/riscv/translate.c                   | 12 ++--
 tests/functional/riscv64/meson.build       |  1 +
 tests/functional/riscv64/test_bigendian.py | 57 +++++++++++++++
 11 files changed, 211 insertions(+), 40 deletions(-)
 create mode 100644 tests/functional/riscv64/test_bigendian.py

-- 
2.34.1

Hi Djordje,

On Tue, Mar 24, 2026 at 04:40:14PM +0000, Djordje Todorovic wrote:
> Adding functional test case for riscv big-endian.
> 
Thanks for the v5 and for adding the functional test
that Philippe requested. The runtime big-endian approach
is the right direction.

However, it looks like the series was developed on top
of Philippe's "[PATCH-for-11.1] target/riscv: Forbid to
use legacy native endianness API" prep series, which
hasn't been merged yet. This causes two build-breaking
issues and apply failures on both master and
riscv-to-apply.next.

For v6, I'd suggest either:
a) Explicitly declare "Based-on:" Philippe's prep
   series, or

b) Include the prerequisite changes (MSTATUS defines,
   op_helper.c cleanup, MO_TE->MO_LE) in this series.

Thanks,
Chao
> Djordje Todorovic (7):
>   target/riscv: Add big-endian CPU property
>   target/riscv: Set endianness MSTATUS bits at CPU reset
>   target/riscv: Implement runtime data endianness via MSTATUS bits
>   hw/riscv: Make boot code endianness-aware at runtime
>   target/riscv: Fix page table walk endianness for big-endian harts
>   target/riscv: Support runtime endianness in virtio via sysemu callback
>   target/riscv: Add test for RISC-V BE
> 
>  hw/riscv/boot.c                            | 82 ++++++++++++++++++----
>  include/hw/riscv/boot.h                    |  2 +
>  target/riscv/cpu.c                         | 22 ++++--
>  target/riscv/cpu.h                         | 28 ++++++++
>  target/riscv/cpu_cfg_fields.h.inc          |  1 +
>  target/riscv/cpu_helper.c                  | 28 ++++++--
>  target/riscv/internals.h                   |  9 +--
>  target/riscv/tcg/tcg-cpu.c                 |  9 ++-
>  target/riscv/translate.c                   | 12 ++--
>  tests/functional/riscv64/meson.build       |  1 +
>  tests/functional/riscv64/test_bigendian.py | 57 +++++++++++++++
>  11 files changed, 211 insertions(+), 40 deletions(-)
>  create mode 100644 tests/functional/riscv64/test_bigendian.py
> 
> -- 
> 2.34.1