[v1] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI

[PATCH] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI

Jay Chang posted 1 patch 1 week, 3 days ago

Diff against v2
Download mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260324052620.36049-1-jay.chang@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

There is a newer version of this series

hw/riscv/riscv-iommu.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)

Expand all Fold all

[PATCH] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI

Posted by Jay Chang 1 week, 3 days ago

Replace the temporary custom extension bit (TC[32]) with the
standard EN_PRI bit defined in RISC-V IOMMU specification.

Signed-off-by: Jay Chang <jay.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 hw/riscv/riscv-iommu.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 225394ea83..7d5c8cd7f5 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
     riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);
 
     iot_cache = g_hash_table_ref(s->iot_cache);
-    /*
-     * TC[32] is reserved for custom extensions, used here to temporarily
-     * enable automatic page-request generation for ATS queries.
-     */
-    enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));
+    enable_pri = (iotlb->perm == IOMMU_NONE) &&
+        (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);
     enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);
 
     /* Check for ATS request. */
-- 
2.48.1

Re: [PATCH] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI

Posted by Nutty.Liu 1 week, 3 days ago

On 3/24/2026 1:26 PM, Jay Chang wrote:
> Replace the temporary custom extension bit (TC[32]) with the
> standard EN_PRI bit defined in RISC-V IOMMU specification.
>
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   hw/riscv/riscv-iommu.c | 7 ++-----
>   1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 225394ea83..7d5c8cd7f5 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
>       riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);
>   
>       iot_cache = g_hash_table_ref(s->iot_cache);
> -    /*
> -     * TC[32] is reserved for custom extensions, used here to temporarily
> -     * enable automatic page-request generation for ATS queries.
> -     */
> -    enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));
> +    enable_pri = (iotlb->perm == IOMMU_NONE) &&
> +        (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);
Better to align with the first word on the right side of '='.  Like:

+    enable_pri = (iotlb->perm == IOMMU_NONE) &&
+                 (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);

Otherwise,
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
>       enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);
>   
>       /* Check for ATS request. */