These devices are only used by the RISC-V targets, which are
only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_LITTLE_ENDIAN (besides, the
DEVICE_BIG_ENDIAN case isn't tested). Simplify directly
using DEVICE_LITTLE_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260318103122.97244-2-philmd@linaro.org>
---
hw/char/ibex_uart.c | 2 +-
hw/char/shakti_uart.c | 2 +-
hw/char/sifive_uart.c | 2 +-
hw/misc/sifive_e_aon.c | 2 +-
hw/misc/sifive_e_prci.c | 2 +-
hw/misc/sifive_u_otp.c | 2 +-
hw/misc/sifive_u_prci.c | 2 +-
hw/riscv/riscv-iommu.c | 2 +-
hw/sd/cadence_sdhci.c | 2 +-
hw/timer/ibex_timer.c | 2 +-
hw/timer/sifive_pwm.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index 127d219df3c..26ed1aea140 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -470,7 +470,7 @@ static void fifo_trigger_update(void *opaque)
static const MemoryRegionOps ibex_uart_ops = {
.read = ibex_uart_read,
.write = ibex_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
index 2d1bc9cb8e2..d38920a03a0 100644
--- a/hw/char/shakti_uart.c
+++ b/hw/char/shakti_uart.c
@@ -103,7 +103,7 @@ static void shakti_uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps shakti_uart_ops = {
.read = shakti_uart_read,
.write = shakti_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {.min_access_size = 1, .max_access_size = 4},
.valid = {.min_access_size = 1, .max_access_size = 4},
};
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 4c30fbf5685..b4de662d616 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -236,7 +236,7 @@ static void fifo_trigger_update(void *opaque)
static const MemoryRegionOps sifive_uart_ops = {
.read = sifive_uart_read,
.write = sifive_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c
index e78f4f56725..ff2a7c18235 100644
--- a/hw/misc/sifive_e_aon.c
+++ b/hw/misc/sifive_e_aon.c
@@ -250,7 +250,7 @@ sifive_e_aon_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_e_aon_ops = {
.read = sifive_e_aon_read,
.write = sifive_e_aon_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
index 400664aabae..a4a60e7b406 100644
--- a/hw/misc/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -75,7 +75,7 @@ static void sifive_e_prci_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_e_prci_ops = {
.read = sifive_e_prci_read,
.write = sifive_e_prci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index 7205374bc39..cececd4f7a8 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -187,7 +187,7 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_u_otp_ops = {
.read = sifive_u_otp_read,
.write = sifive_u_otp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
index f51588623ab..4674d5925ea 100644
--- a/hw/misc/sifive_u_prci.c
+++ b/hw/misc/sifive_u_prci.c
@@ -112,7 +112,7 @@ static void sifive_u_prci_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_u_prci_ops = {
.read = sifive_u_prci_read,
.write = sifive_u_prci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 225394ea838..c3c9ed6469a 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2375,7 +2375,7 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
static const MemoryRegionOps riscv_iommu_mmio_ops = {
.read_with_attrs = riscv_iommu_mmio_read,
.write_with_attrs = riscv_iommu_mmio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 8,
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
index d576855a1a8..8476baf67fb 100644
--- a/hw/sd/cadence_sdhci.c
+++ b/hw/sd/cadence_sdhci.c
@@ -122,7 +122,7 @@ static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps cadence_sdhci_ops = {
.read = cadence_sdhci_read,
.write = cadence_sdhci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index ee186521893..0f12531934d 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -234,7 +234,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps ibex_timer_ops = {
.read = ibex_timer_read,
.write = ibex_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c
index 780eaa50799..4f4f566cd4b 100644
--- a/hw/timer/sifive_pwm.c
+++ b/hw/timer/sifive_pwm.c
@@ -388,7 +388,7 @@ static void sifive_pwm_reset(DeviceState *dev)
static const MemoryRegionOps sifive_pwm_ops = {
.read = sifive_pwm_read,
.write = sifive_pwm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_sifive_pwm = {
--
2.53.0