[v3] target/riscv: corner case fixes

[PATCH v3 0/3] target/riscv: corner case fixes

Nicholas Piggin posted 3 patches 21 hours ago

Diff against v1 v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/20260321144554.606417-1-npiggin@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/csr.c                        |  16 +-
target/riscv/vector_helper.c              |   2 +
tests/tcg/riscv64/Makefile.softmmu-target |   5 +
tests/tcg/riscv64/Makefile.target         |  16 ++
tests/tcg/riscv64/misa-ialign.S           |  88 ++++++
tests/tcg/riscv64/test-interrupted-v.c    | 329 ++++++++++++++++++++++
tests/tcg/riscv64/test-vstart-overflow.c  |  78 +++++
7 files changed, 531 insertions(+), 3 deletions(-)
create mode 100644 tests/tcg/riscv64/misa-ialign.S
create mode 100644 tests/tcg/riscv64/test-interrupted-v.c
create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c

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[PATCH v3 0/3] target/riscv: corner case fixes

Posted by Nicholas Piggin 21 hours ago

Changes:
v3:
* Added vloxei8.v to overflow test.
* Added store variants of interrupted vector ops tests.

v2:
* Added a tcg tests build-time check for vector intrinsics support
  in target compiler before building new tests that require it.
  ci images may not support these yet unfortunately, but upgrading
  those will be a separate effort.

Thanks,
Nick


Nicholas Piggin (3):
  target/riscv: Fix IALIGN check in misa write
  target/riscv: Fix vector whole ldst vstart check
  tests/tcg: Add riscv test for interrupted vector ops

 target/riscv/csr.c                        |  16 +-
 target/riscv/vector_helper.c              |   2 +
 tests/tcg/riscv64/Makefile.softmmu-target |   5 +
 tests/tcg/riscv64/Makefile.target         |  16 ++
 tests/tcg/riscv64/misa-ialign.S           |  88 ++++++
 tests/tcg/riscv64/test-interrupted-v.c    | 329 ++++++++++++++++++++++
 tests/tcg/riscv64/test-vstart-overflow.c  |  78 +++++
 7 files changed, 531 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/riscv64/misa-ialign.S
 create mode 100644 tests/tcg/riscv64/test-interrupted-v.c
 create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c

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2.51.0