target/riscv: add draft RISC-V Zbr ext as xbr0p93

[PATCH v5 0/3] target/riscv: add draft RISC-V Zbr ext as xbr0p93

James Wainwright posted 3 patches 1 day, 22 hours ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260320134254.217123-1-james.wainwright@lowrisc.org

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Weiwei Li <liwei1518@gmail.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

MAINTAINERS                               |  5 +-
disas/meson.build                         |  3 +-
disas/riscv-xlrbr.c                       | 79 ++++++++++++++++++++++
disas/riscv-xlrbr.h                       | 19 ++++++
disas/riscv.c                             |  2 +
include/qemu/crc32.h                      | 14 ++++
include/qemu/crc32c.h                     |  1 +
target/riscv/bitmanip_helper.c            | 20 ++++++
target/riscv/cpu.c                        |  4 +-
target/riscv/cpu_cfg.h                    |  1 +
target/riscv/cpu_cfg_fields.h.inc         |  1 +
target/riscv/helper.h                     |  2 +
target/riscv/insn_trans/trans_xlrbr.c.inc | 45 +++++++++++++
target/riscv/meson.build                  |  1 +
target/riscv/translate.c                  |  3 +
target/riscv/xlrbr.decode                 | 30 +++++++++
tests/tcg/riscv64/Makefile.softmmu-target |  5 ++
tests/tcg/riscv64/test-crc32.S            | 64 ++++++++++++++++++
util/crc32.c                              | 81 +++++++++++++++++++++++
util/crc32c.c                             |  4 +-
util/meson.build                          |  1 +
21 files changed, 380 insertions(+), 5 deletions(-)
create mode 100644 disas/riscv-xlrbr.c
create mode 100644 disas/riscv-xlrbr.h
create mode 100644 include/qemu/crc32.h
create mode 100644 target/riscv/insn_trans/trans_xlrbr.c.inc
create mode 100644 target/riscv/xlrbr.decode
create mode 100644 tests/tcg/riscv64/test-crc32.S
create mode 100644 util/crc32.c

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[PATCH v5 0/3] target/riscv: add draft RISC-V Zbr ext as xbr0p93

Posted by James Wainwright 1 day, 22 hours ago

>  This patch fails checkpatch:

Oops, sorry about that. Fixed the license header but the original
`crc32c` file didn't have a `MAINTAINER` so I haven't assigned one to
this new file either. I hope that's okay.

> Please keep previous tags in new versions

Do you mean the `Reviewed-by` lines? I've kept those in this series.

James Wainwright (3):
  util: export CRC32[C] lookup tables
  target/riscv: add draft RISC-V Zbr ext as xbr0p93
  disas: diassemble RISC-V xlrbr (crc32) instructions

 MAINTAINERS                               |  5 +-
 disas/meson.build                         |  3 +-
 disas/riscv-xlrbr.c                       | 79 ++++++++++++++++++++++
 disas/riscv-xlrbr.h                       | 19 ++++++
 disas/riscv.c                             |  2 +
 include/qemu/crc32.h                      | 14 ++++
 include/qemu/crc32c.h                     |  1 +
 target/riscv/bitmanip_helper.c            | 20 ++++++
 target/riscv/cpu.c                        |  4 +-
 target/riscv/cpu_cfg.h                    |  1 +
 target/riscv/cpu_cfg_fields.h.inc         |  1 +
 target/riscv/helper.h                     |  2 +
 target/riscv/insn_trans/trans_xlrbr.c.inc | 45 +++++++++++++
 target/riscv/meson.build                  |  1 +
 target/riscv/translate.c                  |  3 +
 target/riscv/xlrbr.decode                 | 30 +++++++++
 tests/tcg/riscv64/Makefile.softmmu-target |  5 ++
 tests/tcg/riscv64/test-crc32.S            | 64 ++++++++++++++++++
 util/crc32.c                              | 81 +++++++++++++++++++++++
 util/crc32c.c                             |  4 +-
 util/meson.build                          |  1 +
 21 files changed, 380 insertions(+), 5 deletions(-)
 create mode 100644 disas/riscv-xlrbr.c
 create mode 100644 disas/riscv-xlrbr.h
 create mode 100644 include/qemu/crc32.h
 create mode 100644 target/riscv/insn_trans/trans_xlrbr.c.inc
 create mode 100644 target/riscv/xlrbr.decode
 create mode 100644 tests/tcg/riscv64/test-crc32.S
 create mode 100644 util/crc32.c

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2.48.1