Added a little comment to explain the RADDR<->ra mismatch.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/syndrome.h | 38 +++++++++++++++++++++++++++++++++-----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 503b19b5d02..76f66b3beef 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -690,21 +690,49 @@ static inline uint32_t syn_pcalignment(void)
return res;
}
+/*
+ * ISS encoding for a GCS exception
+ *
+ * Field validity depends on EXTYPE
+ */
+FIELD(GCS_ISS, IT, 0, 5)
+FIELD(GCS_ISS, RN, 5, 5) /* only for non EXLOCK exceptions */
+FIELD(GCS_ISS, RADDR, 10, 5) /* only for GCSSTR/GCSSTTR traps */
+FIELD(GCS_ISS, EXTYPE, 20, 4)
+
static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn)
{
- return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL |
- (GCS_ET_DataCheck << 20) | (rn << 5) | it);
+ uint32_t res = syn_set_ec(0, EC_GCS);
+ res = FIELD_DP32(res, SYNDROME, IL, 1);
+
+ res = FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_DataCheck);
+ res = FIELD_DP32(res, GCS_ISS, RN, rn);
+ res = FIELD_DP32(res, GCS_ISS, IT, it);
+
+ return res;
}
static inline uint32_t syn_gcs_exlock(void)
{
- return (EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | (GCS_ET_EXLOCK << 20);
+ uint32_t res = syn_set_ec(0, EC_GCS);
+ res = FIELD_DP32(res, SYNDROME, IL, 1);
+
+ res = FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_EXLOCK);
+
+ return res;
}
static inline uint32_t syn_gcs_gcsstr(int ra, int rn)
{
- return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL |
- (GCS_ET_GCSSTR_GCSSTTR << 20) | (ra << 10) | (rn << 5));
+ uint32_t res = syn_set_ec(0, EC_GCS);
+ res = FIELD_DP32(res, SYNDROME, IL, 1);
+
+ res = FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_GCSSTR_GCSSTTR);
+ /* when ExType == 0b0010 RADDR is the data register */
+ res = FIELD_DP32(res, GCS_ISS, RADDR, ra);
+ res = FIELD_DP32(res, GCS_ISS, RN, rn);
+
+ return res;
}
static inline uint32_t syn_serror(uint32_t extra)
--
2.47.3