[v1] riscv-to-apply queue

[PULL 00/17] riscv-to-apply queue

alistair23@gmail.com posted 17 patches 2 days, 13 hours ago

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Maintainers: Pierrick Bouvier <pierrick.bouvier@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Peter Maydell <peter.maydell@linaro.org>, "Alex Bennée" <alex.bennee@linaro.org>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

There is a newer version of this series

MAINTAINERS                       |  4 +++-
docs/about/deprecated.rst         | 11 ----------
docs/about/removed-features.rst   | 11 ++++++++++
include/hw/char/sifive_uart.h     |  3 ++-
include/hw/riscv/cps.h            |  2 +-
target/riscv/pmp.h                |  1 +
target/riscv/cpu_cfg_fields.h.inc |  1 +
hw/char/sifive_uart.c             | 46 +++++++++++++++++++++++++++++++--------
hw/dma/sifive_pdma.c              |  1 +
hw/riscv/riscv-iommu.c            | 16 +++++++++++---
hw/riscv/virt.c                   |  9 --------
target/riscv/cpu.c                |  3 +++
target/riscv/csr.c                | 16 ++++++++++++--
target/riscv/pmp.c                | 16 ++++++++++++++
target/riscv/vector_helper.c      | 23 ++++++--------------
fpu/softfloat-parts.c.inc         |  4 +++-
16 files changed, 113 insertions(+), 54 deletions(-)

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[PULL 00/17] riscv-to-apply queue

Posted by alistair23@gmail.com 2 days, 13 hours ago

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 5a68a3add61208aad34d47134fdcfd3f407d2ce4:

  Update version for v11.0.0-rc0 release (2026-03-18 15:56:51 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260320

for you to fetch changes up to 38937473da3ebdd89bbe6bbc3effc0b153ceb414:

  target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode (2026-03-20 08:41:15 +1000)

----------------------------------------------------------------
RISC-V PR for 11.

* Fix integer overflow in cm_base calculation
* Fix null pointer dereference in cpu_set_exception_base
* Update Daniel Henrique Barboza's email
* Add Chao Liu as reviewer
* Set SiFive PDMA done bit upon completion
* Remove deprecated 'riscv, delegate' device-tree property
* Fix OCP FP8 E4M3 conversion issues
* Fix IOMMU instance_init allocations in instance_finalize
* Support Smpmpmt extension
* Fix SiFive UART spurious IRQ issue and misc updates
* Fix missing flags merge in probe_pages for cross-page accesses
* Fix page probe issues in vext_ldff
* Fix scountovf CSR behavior in VS-mode and M-mode

----------------------------------------------------------------
Chao Liu (1):
      MAINTAINERS: Add myself as a reviewer for RISC-V TCG CPUs

Daniel Henrique Barboza (1):
      MAINTAINERS: update my email

Djordje Todorovic (2):
      hw/riscv: Fix integer overflow in cm_base calculation
      target/riscv: Fix null pointer dereference in cpu_set_exception_base

Frank Chang (4):
      hw/char: sifive_uart: Implement txctrl.txen and rxctrl.rxen
      hw/char: sifive_uart: Sync txwm interrupt pending status after TX FIFO enqueue
      hw/char: sifive_uart: Update IRQ when rxctrl is written
      hw/char: sifive_uart: Remove ip variable

Jay Chang (2):
      hw/dma: sifive_pdma: Set done bit upon completion
      target/riscv: Support Smpmpmt extension

Jim Shu (1):
      target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode

Max Chou (4):
      fpu: Fix repacking issues in the uncanonical step for E4M3 overflow
      fpu: Fix unexpected exception flags when converting infinity to OCP E4M3
      target/riscv: rvv: Fix missing flags merge in probe_pages for cross-page accesses
      target/riscv: rvv: Fix page probe issues in vext_ldff

Peter Maydell (1):
      hw/riscv/riscv-iommu: Free instance_init allocations in instance_finalize

Philippe Mathieu-Daudé (1):
      hw/riscv: Remove deprecated 'riscv, delegate' device-tree property

 MAINTAINERS                       |  4 +++-
 docs/about/deprecated.rst         | 11 ----------
 docs/about/removed-features.rst   | 11 ++++++++++
 include/hw/char/sifive_uart.h     |  3 ++-
 include/hw/riscv/cps.h            |  2 +-
 target/riscv/pmp.h                |  1 +
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 hw/char/sifive_uart.c             | 46 +++++++++++++++++++++++++++++++--------
 hw/dma/sifive_pdma.c              |  1 +
 hw/riscv/riscv-iommu.c            | 16 +++++++++++---
 hw/riscv/virt.c                   |  9 --------
 target/riscv/cpu.c                |  3 +++
 target/riscv/csr.c                | 16 ++++++++++++--
 target/riscv/pmp.c                | 16 ++++++++++++++
 target/riscv/vector_helper.c      | 23 ++++++--------------
 fpu/softfloat-parts.c.inc         |  4 +++-
 16 files changed, 113 insertions(+), 54 deletions(-)

Re: [PULL 00/17] riscv-to-apply queue

Posted by Peter Maydell 2 days ago

On Thu, 19 Mar 2026 at 23:27, <alistair23@gmail.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 5a68a3add61208aad34d47134fdcfd3f407d2ce4:
>
>   Update version for v11.0.0-rc0 release (2026-03-18 15:56:51 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260320
>
> for you to fetch changes up to 38937473da3ebdd89bbe6bbc3effc0b153ceb414:
>
>   target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode (2026-03-20 08:41:15 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 11.
>
> * Fix integer overflow in cm_base calculation
> * Fix null pointer dereference in cpu_set_exception_base
> * Update Daniel Henrique Barboza's email
> * Add Chao Liu as reviewer
> * Set SiFive PDMA done bit upon completion
> * Remove deprecated 'riscv, delegate' device-tree property
> * Fix OCP FP8 E4M3 conversion issues
> * Fix IOMMU instance_init allocations in instance_finalize
> * Support Smpmpmt extension
> * Fix SiFive UART spurious IRQ issue and misc updates
> * Fix missing flags merge in probe_pages for cross-page accesses
> * Fix page probe issues in vext_ldff
> * Fix scountovf CSR behavior in VS-mode and M-mode
>
> ----------------------------------------------------------------



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/11.0
for any user-visible changes.

-- PMM