Flush TLB on write to any MECID register. This allow us to take the slow
path and check if the MECID is the correct.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
---
 target/arm/helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6bfab90981..ec25ec8444 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5125,6 +5125,8 @@ static CPAccessResult mecid_access(CPUARMState *env,
 static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
+    tlb_flush(CPU(env_archcpu(env)));
+
     value = extract64(value, 0, MECID_WIDTH);
     raw_write(env, ri, value);
 }
-- 
2.34.1

On 3/19/26 12:23, Gustavo Romero wrote:
> Flush TLB on write to any MECID register. This allow us to take the slow
> path and check if the MECID is the correct.
> 
> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
> ---
>   target/arm/helper.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 6bfab90981..ec25ec8444 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -5125,6 +5125,8 @@ static CPAccessResult mecid_access(CPUARMState *env,
>   static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                           uint64_t value)
>   {
> +    tlb_flush(CPU(env_archcpu(env)));
> +
>       value = extract64(value, 0, MECID_WIDTH);
>       raw_write(env, ri, value);
>   }

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~