Implements RISC-V S-mode Physical Memory Protection (SPMP) and its extensions

[RFC PATCH 0/6] Implements RISC-V S-mode Physical Memory Protection (SPMP) and its extensions

luisccc posted 6 patches 2 weeks, 4 days ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260318185238.99143-1-luisccunha8@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c                |  88 +++++
target/riscv/cpu.h                |   9 +
target/riscv/cpu_bits.h           |   9 +
target/riscv/cpu_cfg_fields.h.inc |   3 +
target/riscv/cpu_helper.c         | 139 ++++++--
target/riscv/csr.c                | 167 ++++++++++
target/riscv/meson.build          |   1 +
target/riscv/pmp.c                |  14 +-
target/riscv/pmp.h                |   1 +
target/riscv/spmp.c               | 516 ++++++++++++++++++++++++++++++
target/riscv/spmp.h               |  83 +++++
11 files changed, 1005 insertions(+), 25 deletions(-)
create mode 100644 target/riscv/spmp.c
create mode 100644 target/riscv/spmp.h

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[RFC PATCH 0/6] Implements RISC-V S-mode Physical Memory Protection (SPMP) and its extensions

Posted by luisccc 2 weeks, 4 days ago

This patchset adds initial support for RISC-V S-mode Physical Memory Protection (SPMP) to QEMU.

Implemented version of the specification:
https://github.com/riscv/riscv-isa-manual/tree/d539cf2fe65b02a734bf97f210474f82bd5e9393

The implementation introduces the SPMP checks to the core, CSR support, delegation handling, and CPU properties to enable SPMP and corresponding extensions.

SPMP can be enabled via:
  -cpu <model>,spmp=true
Note: smpmpdeleg, sscsrind, and smcsrind also enabled.

The sspmpen extension can be enabled via:
  -cpu <model>,sspmpen=true
Note: SPMP and its depedencies also enabled.

luisccc (6):
  target/riscv: Add SPMP infrastructure
  target/riscv: Add SPMP CSR configuration
  target/riscv: Implement extension for Sharing Hardware Resources
    (Smpmpdeleg)
  target/riscv: Implement extension for Optimizing Context Switching
    (Sspmpen)
  target/riscv: Enable SPMP support in CPU
  target/riscv: Add CPU properties for SPMP and sspmpen

 target/riscv/cpu.c                |  88 +++++
 target/riscv/cpu.h                |   9 +
 target/riscv/cpu_bits.h           |   9 +
 target/riscv/cpu_cfg_fields.h.inc |   3 +
 target/riscv/cpu_helper.c         | 139 ++++++--
 target/riscv/csr.c                | 167 ++++++++++
 target/riscv/meson.build          |   1 +
 target/riscv/pmp.c                |  14 +-
 target/riscv/pmp.h                |   1 +
 target/riscv/spmp.c               | 516 ++++++++++++++++++++++++++++++
 target/riscv/spmp.h               |  83 +++++
 11 files changed, 1005 insertions(+), 25 deletions(-)
 create mode 100644 target/riscv/spmp.c
 create mode 100644 target/riscv/spmp.h

-- 
2.43.0