target/riscv: Forbid to use legacy native endianness API

[PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register()

Posted by Philippe Mathieu-Daudé 2 weeks, 5 days ago

Use a single ldn() call, sign-extend once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Note I'm skeptical about 128-bit registers path, but this
would be a pre-existing issue.
---
 target/riscv/gdbstub.c | 25 ++++++-------------------
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index be42566bcc8..a5c12638782 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -84,33 +84,20 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    int length = 0;
-    uint64_t tmp;
+    const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8;
+    uint64_t tmp = ldn(env, mem_buf, regsize);
 
-    switch (mcc->def->misa_mxl_max) {
-    case MXL_RV32:
-        tmp = (int32_t)ldn(env, mem_buf, 4);
-        length = 4;
-        break;
-    case MXL_RV64:
-    case MXL_RV128:
-        if (env->xl < MXL_RV64) {
-            tmp = (int32_t)ldn(env, mem_buf, 8);
-        } else {
-            tmp = ldn(env, mem_buf, 8);
-        }
-        length = 8;
-        break;
-    default:
-        g_assert_not_reached();
+    if (env->xl < MXL_RV64) {
+        tmp = (int32_t)tmp;
     }
+
     if (n > 0 && n < 32) {
         env->gpr[n] = tmp;
     } else if (n == 32) {
         env->pc = tmp;
     }
 
-    return length;
+    return regsize;
 }
 
 static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
-- 
2.53.0

Re: [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register()

Posted by Alistair Francis 1 week, 4 days ago

On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Use a single ldn() call, sign-extend once.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
> Note I'm skeptical about 128-bit registers path, but this
> would be a pre-existing issue.
> ---
>  target/riscv/gdbstub.c | 25 ++++++-------------------
>  1 file changed, 6 insertions(+), 19 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index be42566bcc8..a5c12638782 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -84,33 +84,20 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
>      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
> -    int length = 0;
> -    uint64_t tmp;
> +    const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8;
> +    uint64_t tmp = ldn(env, mem_buf, regsize);
>
> -    switch (mcc->def->misa_mxl_max) {
> -    case MXL_RV32:
> -        tmp = (int32_t)ldn(env, mem_buf, 4);
> -        length = 4;
> -        break;
> -    case MXL_RV64:
> -    case MXL_RV128:
> -        if (env->xl < MXL_RV64) {
> -            tmp = (int32_t)ldn(env, mem_buf, 8);
> -        } else {
> -            tmp = ldn(env, mem_buf, 8);
> -        }
> -        length = 8;
> -        break;
> -    default:
> -        g_assert_not_reached();
> +    if (env->xl < MXL_RV64) {
> +        tmp = (int32_t)tmp;
>      }
> +
>      if (n > 0 && n < 32) {
>          env->gpr[n] = tmp;
>      } else if (n == 32) {
>          env->pc = tmp;
>      }
>
> -    return length;
> +    return regsize;
>  }
>
>  static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
> --
> 2.53.0
>
>