target/riscv: Forbid to use legacy native endianness API

[PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release

Posted by Philippe Mathieu-Daudé 2 weeks, 5 days ago

All callers of gen_load_acquire() and gen_store_release() set both
the MO_ALIGN|MO_TE flags. Set them once in each callee.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
index 525f01ca347..2b1f73f650b 100644
--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
@@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
         return false;
     }
 
+    memop |= MO_ALIGN | MO_TE;
     memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
 
     tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
@@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
 static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
 {
     REQUIRE_ZALASR(ctx);
-    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
+    return gen_load_acquire(ctx, a, MO_SB);
 }
 
 static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
 {
     REQUIRE_ZALASR(ctx);
-    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
+    return gen_load_acquire(ctx, a, MO_SW);
 }
 
 static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
 {
     REQUIRE_ZALASR(ctx);
-    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
+    return gen_load_acquire(ctx, a, MO_SL);
 }
 
 static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZALASR(ctx);
-    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
+    return gen_load_acquire(ctx, a, MO_UQ);
 }
 
 static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
@@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
         return false;
     }
 
+    memop |= MO_ALIGN | MO_TE;
     memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
 
     /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
@@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
 static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
 {
     REQUIRE_ZALASR(ctx);
-    return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
+    return gen_store_release(ctx, a, MO_SB);
 }
 
 static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
 {
     REQUIRE_ZALASR(ctx);
-    return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
+    return gen_store_release(ctx, a, MO_SW);
 }
 
 static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
 {
     REQUIRE_ZALASR(ctx);
-    return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
+    return gen_store_release(ctx, a, MO_SL);
 }
 
 static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZALASR(ctx);
-    return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
+    return gen_store_release(ctx, a, MO_UQ);
 }
-- 
2.53.0

Re: [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release

Posted by Alistair Francis 1 week, 4 days ago

On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> All callers of gen_load_acquire() and gen_store_release() set both
> the MO_ALIGN|MO_TE flags. Set them once in each callee.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> index 525f01ca347..2b1f73f650b 100644
> --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> @@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
>          return false;
>      }
>
> +    memop |= MO_ALIGN | MO_TE;
>      memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
>
>      tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
> @@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
>  static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
>  {
>      REQUIRE_ZALASR(ctx);
> -    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
> +    return gen_load_acquire(ctx, a, MO_SB);
>  }
>
>  static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
>  {
>      REQUIRE_ZALASR(ctx);
> -    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> +    return gen_load_acquire(ctx, a, MO_SW);
>  }
>
>  static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
>  {
>      REQUIRE_ZALASR(ctx);
> -    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> +    return gen_load_acquire(ctx, a, MO_SL);
>  }
>
>  static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
>  {
>      REQUIRE_64BIT(ctx);
>      REQUIRE_ZALASR(ctx);
> -    return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> +    return gen_load_acquire(ctx, a, MO_UQ);
>  }
>
>  static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> @@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
>          return false;
>      }
>
> +    memop |= MO_ALIGN | MO_TE;
>      memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
>
>      /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
> @@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
>  static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
>  {
>      REQUIRE_ZALASR(ctx);
> -    return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
> +    return gen_store_release(ctx, a, MO_SB);
>  }
>
>  static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
>  {
>      REQUIRE_ZALASR(ctx);
> -    return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> +    return gen_store_release(ctx, a, MO_SW);
>  }
>
>  static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
>  {
>      REQUIRE_ZALASR(ctx);
> -    return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> +    return gen_store_release(ctx, a, MO_SL);
>  }
>
>  static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
>  {
>      REQUIRE_64BIT(ctx);
>      REQUIRE_ZALASR(ctx);
> -    return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> +    return gen_store_release(ctx, a, MO_UQ);
>  }
> --
> 2.53.0
>
>