target/riscv: Forbid to use legacy native endianness API

[PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model

Posted by Philippe Mathieu-Daudé 2 weeks, 5 days ago

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

We had to check that mttcg was not used when executing QEMU with
-cpu x-rv128 as a single 128-bit access was done as two distinct
64-bit accesses.
Now that we use the 128-bit ld/st that access the data atomically,
this check is no longer necessary.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/tcg/tcg-cpu.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 988b2d905f5..3407191c224 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
     }
 
 #ifndef CONFIG_USER_ONLY
-    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-
-    if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
-        /* Missing 128-bit aligned atomics */
-        error_setg(errp,
-                   "128-bit RISC-V currently does not work with Multi "
-                   "Threaded TCG. Please use: -accel tcg,thread=single");
-        return false;
-    }
-
     CPURISCVState *env = &cpu->env;
 
     tcg_cflags_set(CPU(cs), CF_PCREL);
-- 
2.53.0

Re: [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model

Posted by Alistair Francis 1 week, 4 days ago

On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
>
> We had to check that mttcg was not used when executing QEMU with
> -cpu x-rv128 as a single 128-bit access was done as two distinct
> 64-bit accesses.
> Now that we use the 128-bit ld/st that access the data atomically,
> this check is no longer necessary.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes.fr>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 10 ----------
>  1 file changed, 10 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 988b2d905f5..3407191c224 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
>      }
>
>  #ifndef CONFIG_USER_ONLY
> -    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> -
> -    if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
> -        /* Missing 128-bit aligned atomics */
> -        error_setg(errp,
> -                   "128-bit RISC-V currently does not work with Multi "
> -                   "Threaded TCG. Please use: -accel tcg,thread=single");
> -        return false;
> -    }
> -
>      CPURISCVState *env = &cpu->env;
>
>      tcg_cflags_set(CPU(cs), CF_PCREL);
> --
> 2.53.0
>
>