target/riscv: Forbid to use legacy native endianness API

[PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension)

Posted by Philippe Mathieu-Daudé 2 weeks, 5 days ago

Replace compile-time MO_TE evaluation by runtime mo_endian()
one, which expand target endianness from DisasContext.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
index 445406cf015..f50c52f22c9 100644
--- a/target/riscv/insn_trans/trans_zilsd.c.inc
+++ b/target/riscv/insn_trans/trans_zilsd.c.inc
@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
     TCGv addr = get_address(ctx, a->rs1, a->imm);
     TCGv_i64 tmp = tcg_temp_new_i64();
 
-    tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
+    tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
 
     if (a->rd == 0) {
         return true;
@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
     } else {
         tcg_gen_concat_tl_i64(tmp, data_low, data_high);
     }
-    tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
+    tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
 
     return true;
 }
-- 
2.53.0

Re: [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension)

Posted by Alistair Francis 1 week, 4 days ago

On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Replace compile-time MO_TE evaluation by runtime mo_endian()
> one, which expand target endianness from DisasContext.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
> index 445406cf015..f50c52f22c9 100644
> --- a/target/riscv/insn_trans/trans_zilsd.c.inc
> +++ b/target/riscv/insn_trans/trans_zilsd.c.inc
> @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
>      TCGv addr = get_address(ctx, a->rs1, a->imm);
>      TCGv_i64 tmp = tcg_temp_new_i64();
>
> -    tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
> +    tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
>
>      if (a->rd == 0) {
>          return true;
> @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
>      } else {
>          tcg_gen_concat_tl_i64(tmp, data_low, data_high);
>      }
> -    tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
> +    tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
>
>      return true;
>  }
> --
> 2.53.0
>
>