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  3. [PATCH 0/3] target/ppc: Replace target_ulong -> uint64_t for TARGET_PPC64
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[PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit

Philippe Mathieu-Daudé posted 3 patches 3 weeks, 1 day ago
Maintainers: Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>
[PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit
Posted by Philippe Mathieu-Daudé 3 weeks, 1 day ago 
When TARGET_PPC64 is set, the 'target_ulong' type expand to
the 'uint64_t' one. Use the latter which is more explicity,
similarly with the TCG and migration APIs. No logical change
intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h       | 2 +-
 target/ppc/machine.c   | 2 +-
 target/ppc/translate.c | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 63c8fa25acc..f4438982928 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1298,7 +1298,7 @@ struct CPUArchState {
     target_ulong reserve_length; /* Reservation larx op size (bytes) */
     target_ulong reserve_val;    /* Reservation value */
 #if defined(TARGET_PPC64)
-    target_ulong reserve_val2;
+    uint64_t reserve_val2;
 #endif
 
     /* These are used in supervisor mode only */
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 49cfdc6d674..b44c3ccf0ae 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -682,7 +682,7 @@ static const VMStateDescription vmstate_reservation = {
         VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
         VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
 #if defined(TARGET_PPC64)
-        VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
+        VMSTATE_UINT64(env.reserve_val2, PowerPCCPU),
 #endif
         VMSTATE_END_OF_LIST()
     }
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0fc81570a8b..ecf75c1376e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -76,7 +76,7 @@ static TCGv cpu_reserve;
 static TCGv cpu_reserve_length;
 static TCGv cpu_reserve_val;
 #if defined(TARGET_PPC64)
-static TCGv cpu_reserve_val2;
+static TCGv_i64 cpu_reserve_val2;
 #endif
 static TCGv cpu_fpscr;
 static TCGv_i32 cpu_access_type;
@@ -152,7 +152,7 @@ void ppc_translate_init(void)
                                          offsetof(CPUPPCState, reserve_val),
                                          "reserve_val");
 #if defined(TARGET_PPC64)
-    cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
+    cpu_reserve_val2 = tcg_global_mem_new_i64(tcg_env,
                                           offsetof(CPUPPCState, reserve_val2),
                                           "reserve_val2");
 #endif
-- 
2.53.0
Re: [PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit
Posted by Miles Glenn 2 weeks, 6 days ago 
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Sun, 2026-03-15 at 18:08 +0100, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       | 2 +-
>  target/ppc/machine.c   | 2 +-
>  target/ppc/translate.c | 4 ++--
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 63c8fa25acc..f4438982928 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1298,7 +1298,7 @@ struct CPUArchState {
>      target_ulong reserve_length; /* Reservation larx op size (bytes) */
>      target_ulong reserve_val;    /* Reservation value */
>  #if defined(TARGET_PPC64)
> -    target_ulong reserve_val2;
> +    uint64_t reserve_val2;
>  #endif
>  
>      /* These are used in supervisor mode only */
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index 49cfdc6d674..b44c3ccf0ae 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -682,7 +682,7 @@ static const VMStateDescription vmstate_reservation = {
>          VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
>          VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
>  #if defined(TARGET_PPC64)
> -        VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
> +        VMSTATE_UINT64(env.reserve_val2, PowerPCCPU),
>  #endif
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 0fc81570a8b..ecf75c1376e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -76,7 +76,7 @@ static TCGv cpu_reserve;
>  static TCGv cpu_reserve_length;
>  static TCGv cpu_reserve_val;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_reserve_val2;
> +static TCGv_i64 cpu_reserve_val2;
>  #endif
>  static TCGv cpu_fpscr;
>  static TCGv_i32 cpu_access_type;
> @@ -152,7 +152,7 @@ void ppc_translate_init(void)
>                                           offsetof(CPUPPCState, reserve_val),
>                                           "reserve_val");
>  #if defined(TARGET_PPC64)
> -    cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
> +    cpu_reserve_val2 = tcg_global_mem_new_i64(tcg_env,
>                                            offsetof(CPUPPCState, reserve_val2),
>                                            "reserve_val2");
>  #endif
Re: [PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit
Posted by Anton Johansson via qemu development 3 weeks ago 
On 15/03/26, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       | 2 +-
>  target/ppc/machine.c   | 2 +-
>  target/ppc/translate.c | 4 ++--
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 63c8fa25acc..f4438982928 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1298,7 +1298,7 @@ struct CPUArchState {
>      target_ulong reserve_length; /* Reservation larx op size (bytes) */
>      target_ulong reserve_val;    /* Reservation value */
>  #if defined(TARGET_PPC64)
> -    target_ulong reserve_val2;
> +    uint64_t reserve_val2;
>  #endif
>  
>      /* These are used in supervisor mode only */
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index 49cfdc6d674..b44c3ccf0ae 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -682,7 +682,7 @@ static const VMStateDescription vmstate_reservation = {
>          VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
>          VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
>  #if defined(TARGET_PPC64)
> -        VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
> +        VMSTATE_UINT64(env.reserve_val2, PowerPCCPU),
>  #endif
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 0fc81570a8b..ecf75c1376e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -76,7 +76,7 @@ static TCGv cpu_reserve;
>  static TCGv cpu_reserve_length;
>  static TCGv cpu_reserve_val;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_reserve_val2;
> +static TCGv_i64 cpu_reserve_val2;
>  #endif
>  static TCGv cpu_fpscr;
>  static TCGv_i32 cpu_access_type;
> @@ -152,7 +152,7 @@ void ppc_translate_init(void)
>                                           offsetof(CPUPPCState, reserve_val),
>                                           "reserve_val");
>  #if defined(TARGET_PPC64)
> -    cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
> +    cpu_reserve_val2 = tcg_global_mem_new_i64(tcg_env,
>                                            offsetof(CPUPPCState, reserve_val2),
>                                            "reserve_val2");
>  #endif
> -- 
> 2.53.0
> 
> 

There's a use left in gen_stqcx_()

    tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);

since the entire function is guarded by TARGET_PPC64 we can just use
tcg_gen_*_i64() throughout?

Otherwise,

Reviewed-by: Anton Johansson <anjo@rev.ng>

Patchew 2.1-devel-ea86937

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