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  3. [PATCH 0/3] target/ppc: Replace target_ulong -> uint64_t for TARGET_PPC64
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[PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit

Philippe Mathieu-Daudé posted 3 patches 3 weeks, 1 day ago
Maintainers: Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>
[PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit
Posted by Philippe Mathieu-Daudé 3 weeks, 1 day ago 
The Come-From Address Register (CFAR) register is only available
on 64-bit CPUs, and is 64-bit wide. Prefer the 64-bit APIs over
the 'target-long' one. No logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h       |  2 +-
 target/ppc/translate.c | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index aba8109bbba..63c8fa25acc 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1285,7 +1285,7 @@ struct CPUArchState {
     target_ulong ctr;
     uint32_t crf[8];       /* condition register */
 #if defined(TARGET_PPC64)
-    target_ulong cfar;
+    uint64_t cfar;
 #endif
     target_ulong xer;      /* XER (with SO, OV, CA split out) */
     target_ulong so;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f26b0281737..0fc81570a8b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -69,7 +69,7 @@ static TCGv cpu_msr;
 static TCGv cpu_ctr;
 static TCGv cpu_lr;
 #if defined(TARGET_PPC64)
-static TCGv cpu_cfar;
+static TCGv_i64 cpu_cfar;
 #endif
 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
 static TCGv cpu_reserve;
@@ -124,8 +124,8 @@ void ppc_translate_init(void)
                                 offsetof(CPUPPCState, lr), "lr");
 
 #if defined(TARGET_PPC64)
-    cpu_cfar = tcg_global_mem_new(tcg_env,
-                                  offsetof(CPUPPCState, cfar), "cfar");
+    cpu_cfar = tcg_global_mem_new_i64(tcg_env,
+                                    offsetof(CPUPPCState, cfar), "cfar");
 #endif
 
     cpu_xer = tcg_global_mem_new(tcg_env,
@@ -626,12 +626,12 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
 /* CFAR */
 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
 {
-    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
+    tcg_gen_mov_i64(cpu_gpr[gprn], cpu_cfar);
 }
 
 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
 {
-    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
+    tcg_gen_mov_i64(cpu_cfar, cpu_gpr[gprn]);
 }
 
 /* Breakpoint */
-- 
2.53.0
Re: [PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit
Posted by Miles Glenn 2 weeks, 6 days ago 
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Sun, 2026-03-15 at 18:08 +0100, Philippe Mathieu-Daudé wrote:
> The Come-From Address Register (CFAR) register is only available
> on 64-bit CPUs, and is 64-bit wide. Prefer the 64-bit APIs over
> the 'target-long' one. No logical change intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       |  2 +-
>  target/ppc/translate.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index aba8109bbba..63c8fa25acc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1285,7 +1285,7 @@ struct CPUArchState {
>      target_ulong ctr;
>      uint32_t crf[8];       /* condition register */
>  #if defined(TARGET_PPC64)
> -    target_ulong cfar;
> +    uint64_t cfar;
>  #endif
>      target_ulong xer;      /* XER (with SO, OV, CA split out) */
>      target_ulong so;
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f26b0281737..0fc81570a8b 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -69,7 +69,7 @@ static TCGv cpu_msr;
>  static TCGv cpu_ctr;
>  static TCGv cpu_lr;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_cfar;
> +static TCGv_i64 cpu_cfar;
>  #endif
>  static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
>  static TCGv cpu_reserve;
> @@ -124,8 +124,8 @@ void ppc_translate_init(void)
>                                  offsetof(CPUPPCState, lr), "lr");
>  
>  #if defined(TARGET_PPC64)
> -    cpu_cfar = tcg_global_mem_new(tcg_env,
> -                                  offsetof(CPUPPCState, cfar), "cfar");
> +    cpu_cfar = tcg_global_mem_new_i64(tcg_env,
> +                                    offsetof(CPUPPCState, cfar), "cfar");
>  #endif
>  
>      cpu_xer = tcg_global_mem_new(tcg_env,
> @@ -626,12 +626,12 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
>  /* CFAR */
>  void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
>  {
> -    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> +    tcg_gen_mov_i64(cpu_gpr[gprn], cpu_cfar);
>  }
>  
>  void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
>  {
> -    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> +    tcg_gen_mov_i64(cpu_cfar, cpu_gpr[gprn]);
>  }
>  
>  /* Breakpoint */
Re: [PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit
Posted by Anton Johansson via qemu development 3 weeks ago 
On 15/03/26, Philippe Mathieu-Daudé wrote:
> The Come-From Address Register (CFAR) register is only available
> on 64-bit CPUs, and is 64-bit wide. Prefer the 64-bit APIs over
> the 'target-long' one. No logical change intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       |  2 +-
>  target/ppc/translate.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index aba8109bbba..63c8fa25acc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1285,7 +1285,7 @@ struct CPUArchState {
>      target_ulong ctr;
>      uint32_t crf[8];       /* condition register */
>  #if defined(TARGET_PPC64)
> -    target_ulong cfar;
> +    uint64_t cfar;
>  #endif
>      target_ulong xer;      /* XER (with SO, OV, CA split out) */
>      target_ulong so;
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f26b0281737..0fc81570a8b 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -69,7 +69,7 @@ static TCGv cpu_msr;
>  static TCGv cpu_ctr;
>  static TCGv cpu_lr;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_cfar;
> +static TCGv_i64 cpu_cfar;
>  #endif
>  static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
>  static TCGv cpu_reserve;
> @@ -124,8 +124,8 @@ void ppc_translate_init(void)
>                                  offsetof(CPUPPCState, lr), "lr");
>  
>  #if defined(TARGET_PPC64)
> -    cpu_cfar = tcg_global_mem_new(tcg_env,
> -                                  offsetof(CPUPPCState, cfar), "cfar");
> +    cpu_cfar = tcg_global_mem_new_i64(tcg_env,
> +                                    offsetof(CPUPPCState, cfar), "cfar");
>  #endif
>  
>      cpu_xer = tcg_global_mem_new(tcg_env,
> @@ -626,12 +626,12 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
>  /* CFAR */
>  void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
>  {
> -    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> +    tcg_gen_mov_i64(cpu_gpr[gprn], cpu_cfar);
>  }
>  
>  void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
>  {
> -    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> +    tcg_gen_mov_i64(cpu_cfar, cpu_gpr[gprn]);
>  }
>  
>  /* Breakpoint */
> -- 
> 2.53.0
> 
> 

Change of 

  - tcg_gen_movi_tl(cpu_cfar, nip);
  + tcg_gen_movi_i64(cpu_cfar, nip);

in gen_update_branch_history() should be in this patch and not the last
one, I'm guessing you just missed it when splitting.

Other than that

Reviewed-by: Anton Johansson <anjo@rev.ng>

Patchew 2.1-devel-ea86937

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