An issue in the page walking code where hugepage mappings were reported as
4K pages in certain configurations was reported by David Hoppenbrouwers in:
https://lore.kernel.org/qemu-devel/20260225145831.28275-1-qemu@demindiro.com/

While the change proposed in that thread fixes that specific bug, there are
opportunities to simplify the algorithm by using a 1-based level accounting
(matching DTE[Mode] and PTE NextLevel semantics).

The second change enforces a rule from the AMD-Vi specification which
requires that NextLevel must be strictly lower than the current level to
guarantee that the page walk eventually completes.

These changes make the page walk logic easier to follow, keep page size
tracking aligned with the current page table level, and prevent invalid
guest tables from causing page walk loops.

For stable: Please pick both patches together, PATCH 2 can be squashed into
PATCH 1 for ease of backporting.

Thank you David and Sairaj for the detailed reporting/analysis of the
original issue and the proposed fixes.

Alejandro

Alejandro Jimenez (2):
  amd_iommu: Follow root pointer before page walk and use 1-based levels
  amd_iommu: Reject non-decreasing NextLevel in fetch_pte()

 hw/i386/amd_iommu.c | 136 +++++++++++++++++++++++++++++++-------------
 hw/i386/amd_iommu.h |  11 ++--
 2 files changed, 101 insertions(+), 46 deletions(-)


base-commit: 1fd5ff9d76d23ab23a68419cbc76d5ee33e8b455
-- 
2.47.3