[v3] target/i386: add compat for migrating error code

[PATCH v3] target/i386: add compat for migrating error code

Fiona Ebner posted 1 patch 3 weeks, 6 days ago

Diff against v2
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260311161053.704233-1-f.ebner@proxmox.com

Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, Eduardo Habkost <eduardo@habkost.net>, "Michael S. Tsirkin" <mst@redhat.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, Zhao Liu <zhao1.liu@intel.com>

hw/i386/pc.c          | 1 +
target/i386/cpu.c     | 1 +
target/i386/cpu.h     | 5 +++++
target/i386/machine.c | 2 +-
4 files changed, 8 insertions(+), 1 deletion(-)

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[PATCH v3] target/i386: add compat for migrating error code

Posted by Fiona Ebner 3 weeks, 6 days ago

If cpu->env.has_error_code is true, backwards migration of a VM from
a QEMU binary with commit 27535e9cca to a QEMU binary without commit
27535e9cca will fail:

> kvm: error while loading state for instance 0x0 of device 'cpu'

In practice, wrongly setting the error code to 0 on the target is
often unproblematic, so additionally checking error_code != 0 in
cpu_errcode_needed() is not enough to mitigate the issue. Instead, add
proper machine version compat handling.

Cc: qemu-stable@nongnu.org
Fixes: 27535e9cca ("target/i386: Add support for save/load of exception error code")
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---

Changes in v3:
* Add comment above compatibility flag.
* Add R-b trailer from Zaho Liu.

 hw/i386/pc.c          | 1 +
 target/i386/cpu.c     | 1 +
 target/i386/cpu.h     | 5 +++++
 target/i386/machine.c | 2 +-
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index addf602da0..4b53b5be4a 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -78,6 +78,7 @@ const size_t pc_compat_10_2_len = G_N_ELEMENTS(pc_compat_10_2);
 
 GlobalProperty pc_compat_10_1[] = {
     { "mch", "extended-tseg-mbytes", "16" },
+    { TYPE_X86_CPU, "x-migrate-error-code", "false" },
 };
 const size_t pc_compat_10_1_len = G_N_ELEMENTS(pc_compat_10_1);
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0a29ff805f..abf129c7d5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10561,6 +10561,7 @@ static const Property x86_cpu_properties[] = {
     DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
     DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
                      true),
+    DEFINE_PROP_BOOL("x-migrate-error-code", X86CPU, migrate_error_code, true),
     /*
      * lecacy_cache defaults to true unless the CPU model provides its
      * own cache information (see x86_cpu_load_def()).
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5a62aa6157..e88cdadb18 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2361,6 +2361,11 @@ struct ArchCPU {
     bool expose_tcg;
     bool migratable;
     bool migrate_smi_count;
+    /*
+     * Compatibility bits for old machine types.
+     * If true, allow including env.error_code in migration stream.
+     */
+    bool migrate_error_code;
     uint32_t apic_id;
 
     /* Enables publishing of TSC increment and Local APIC bus frequencies to
diff --git a/target/i386/machine.c b/target/i386/machine.c
index c913961281..48a2a4b319 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -466,7 +466,7 @@ static bool cpu_errcode_needed(void *opaque)
 {
     X86CPU *cpu = opaque;
 
-    return cpu->env.has_error_code != 0;
+    return cpu->env.has_error_code != 0 && cpu->migrate_error_code;
 }
 
 static const VMStateDescription vmstate_error_code = {
-- 
2.47.3