RISC-V instructions are always little-endian regardless of the data
endianness mode configured via mstatus SBE/MBE/UBE bits.

Currently, instruction fetches in decode_opc() and the page boundary
check use mo_endian(ctx), which returns MO_TE. This happens to work
today because RISC-V targets are little-endian only, but is
semantically incorrect and will break once mo_endian() is updated to
respect runtime data endianness for big-endian support.

Use MO_LE explicitly for all instruction fetch paths. Data memory
operations (AMOs, loads/stores via mxl_memop) continue to use
mo_endian(ctx) as they should respect the configured data endianness.
---
 target/riscv/translate.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index cb4f443601..413911f7f9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1255,7 +1255,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
          * additional page fault.
          */
         opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,
-                                    mo_endian(ctx));
+                                    MO_LE);
     } else {
         /*
          * For unaligned pc, instruction preload may trigger additional
@@ -1263,7 +1263,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
          */
         opcode = (uint32_t) translator_lduw_end(env, &ctx->base,
                                                 ctx->base.pc_next,
-                                                mo_endian(ctx));
+                                                MO_LE);
     }
     ctx->ol = ctx->xl;
 
@@ -1285,7 +1285,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
             opcode = deposit32(opcode, 16, 16,
                                translator_lduw_end(env, &ctx->base,
                                                    ctx->base.pc_next + 2,
-                                                   mo_endian(ctx)));
+                                                   MO_LE));
         }
         ctx->opcode = opcode;
 
@@ -1401,7 +1401,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
             if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
                 uint16_t next_insn =
                     translator_lduw_end(env, &ctx->base, ctx->base.pc_next,
-                                        mo_endian(ctx));
+                                        MO_LE);
                 int len = insn_len(next_insn);
 
                 if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
-- 
2.34.1

On Wed, Mar 11, 2026 at 9:59 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> RISC-V instructions are always little-endian regardless of the data
> endianness mode configured via mstatus SBE/MBE/UBE bits.
>
> Currently, instruction fetches in decode_opc() and the page boundary
> check use mo_endian(ctx), which returns MO_TE. This happens to work
> today because RISC-V targets are little-endian only, but is
> semantically incorrect and will break once mo_endian() is updated to
> respect runtime data endianness for big-endian support.
>
> Use MO_LE explicitly for all instruction fetch paths. Data memory
> operations (AMOs, loads/stores via mxl_memop) continue to use
> mo_endian(ctx) as they should respect the configured data endianness.

Missing Signed-off-by

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair


> ---
>  target/riscv/translate.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index cb4f443601..413911f7f9 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1255,7 +1255,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
>           * additional page fault.
>           */
>          opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,
> -                                    mo_endian(ctx));
> +                                    MO_LE);
>      } else {
>          /*
>           * For unaligned pc, instruction preload may trigger additional
> @@ -1263,7 +1263,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
>           */
>          opcode = (uint32_t) translator_lduw_end(env, &ctx->base,
>                                                  ctx->base.pc_next,
> -                                                mo_endian(ctx));
> +                                                MO_LE);
>      }
>      ctx->ol = ctx->xl;
>
> @@ -1285,7 +1285,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
>              opcode = deposit32(opcode, 16, 16,
>                                 translator_lduw_end(env, &ctx->base,
>                                                     ctx->base.pc_next + 2,
> -                                                   mo_endian(ctx)));
> +                                                   MO_LE));
>          }
>          ctx->opcode = opcode;
>
> @@ -1401,7 +1401,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>              if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
>                  uint16_t next_insn =
>                      translator_lduw_end(env, &ctx->base, ctx->base.pc_next,
> -                                        mo_endian(ctx));
> +                                        MO_LE);
>                  int len = insn_len(next_insn);
>
>                  if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
> --
> 2.34.1