- Address comments from reviewers
- Handle both endianness within signle binary
- Rebase on top of main branch

Djordje Todorovic (9):
  target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks
  target/riscv: Use MO_LE for instruction fetch
  target/riscv: Add big-endian CPU property
  target/riscv: Set endianness MSTATUS bits at CPU reset
  target/riscv: Implement runtime data endianness via MSTATUS bits
  hw/riscv: Make boot code endianness-aware at runtime
  target/riscv: Fix page table walk endianness for big-endian harts
  system/memory: Fix subpage endianness for big-endian targets
  hw/virtio: Support runtime endianness in virtio access helpers

 hw/riscv/boot.c                   | 68 +++++++++++++++++++++++++------
 include/hw/riscv/boot.h           |  2 +
 include/hw/virtio/virtio-access.h |  6 ++-
 include/qemu/target-info.h        |  9 ++++
 system/physmem.c                  |  2 +-
 target-info-stub.c                |  8 +++-
 target/riscv/cpu.c                | 16 +++++---
 target/riscv/cpu.h                | 24 +++++++++++
 target/riscv/cpu_bits.h           |  2 +
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 target/riscv/cpu_helper.c         | 26 +++++++++---
 target/riscv/op_helper.c          |  9 +---
 target/riscv/tcg/tcg-cpu.c        |  9 +++-
 target/riscv/translate.c          | 20 ++++-----
 14 files changed, 155 insertions(+), 47 deletions(-)

-- 
2.34.1