The semihosting ABI [1] states:
> Multi-byte values in memory must be formatted as pure little-endian or pure
> big-endian to match the endianness mapping configuration of the processor.

This series ensures that semihosting data is properly byte-swapped if
the guest's CPU is currently in a different runtime-configurable
endianness than the host's CPU. This is done by adding cpu_internal_tswap()
functions and then using them in semihosting/uaccess.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3258
Buglink: https://github.com/taiki-e/semihosting/issues/18

[1]: https://github.com/ARM-software/abi-aa/blob/2025Q1/semihosting/semihosting.rst#the-semihosting-interface

Signed-off-by: Martin Kröning <martin.kroening@eonerc.rwth-aachen.de>
---
Changes in v3:
- Remove target_needs_bswap() check from cpu_internal_tswap()
  Now, only cpu_internal_needs_bswap() is checked.
  This fixes the behavior on a big-endian host where the CPU currently
  is in little-endian mode.
  Thanks for pointing this out, Peter!
- Link to v2: https://lore.kernel.org/qemu-devel/20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de

Changes in v2:
- Rebase and resolve conflicts.
- Rename virtio_is_big_endian to internal_is_big_endian (fist commit).
- Rename new functios from cpu_tswap to cpu_internal_tswap.
- Document exceptions for using these internal functions (virtio and
  semihosting).
- Link to v1: https://lore.kernel.org/qemu-devel/20260106-semihosting-cpu-tswap-v1-0-646576c25f56@eonerc.rwth-aachen.de

---
Martin Kröning (3):
      include/hw/core: Rename virtio_is_big_endian to internal_is_big_endian
      include/exec: Provide the cpu_internal_tswap() functions
      semihosting/uaccess: Use the cpu_internal_tswap() functions

 hw/core/cpu-system.c             |  6 +++---
 hw/virtio/virtio.c               |  2 +-
 include/exec/tswap.h             | 36 ++++++++++++++++++++++++++++++++++++
 include/hw/core/cpu.h            |  4 ++--
 include/hw/core/sysemu-cpu-ops.h |  6 +++---
 include/semihosting/uaccess.h    |  8 ++++----
 target/arm/cpu.c                 |  4 ++--
 target/ppc/cpu_init.c            |  2 +-
 8 files changed, 52 insertions(+), 16 deletions(-)
---
base-commit: 1fd5ff9d76d23ab23a68419cbc76d5ee33e8b455
change-id: 20260106-semihosting-cpu-tswap-b47debe274e2

Best regards,
-- 
Martin Kröning <martin.kroening@eonerc.rwth-aachen.de>

On Wed, 11 Mar 2026 at 16:28, Martin Kröning
<martin.kroening@eonerc.rwth-aachen.de> wrote:
>
> The semihosting ABI [1] states:
> > Multi-byte values in memory must be formatted as pure little-endian or pure
> > big-endian to match the endianness mapping configuration of the processor.
>
> This series ensures that semihosting data is properly byte-swapped if
> the guest's CPU is currently in a different runtime-configurable
> endianness than the host's CPU. This is done by adding cpu_internal_tswap()
> functions and then using them in semihosting/uaccess.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3258
> Buglink: https://github.com/taiki-e/semihosting/issues/18
>
> [1]: https://github.com/ARM-software/abi-aa/blob/2025Q1/semihosting/semihosting.rst#the-semihosting-interface
>
> Signed-off-by: Martin Kröning <martin.kroening@eonerc.rwth-aachen.de>

Applied to target-arm.next, thanks.

-- PMM

On 12/3/26 19:35, Peter Maydell wrote:
> On Wed, 11 Mar 2026 at 16:28, Martin Kröning
> <martin.kroening@eonerc.rwth-aachen.de> wrote:
>>
>> The semihosting ABI [1] states:
>>> Multi-byte values in memory must be formatted as pure little-endian or pure
>>> big-endian to match the endianness mapping configuration of the processor.
>>
>> This series ensures that semihosting data is properly byte-swapped if
>> the guest's CPU is currently in a different runtime-configurable
>> endianness than the host's CPU. This is done by adding cpu_internal_tswap()
>> functions and then using them in semihosting/uaccess.
>>
>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3258
>> Buglink: https://github.com/taiki-e/semihosting/issues/18
>>
>> [1]: https://github.com/ARM-software/abi-aa/blob/2025Q1/semihosting/semihosting.rst#the-semihosting-interface
>>
>> Signed-off-by: Martin Kröning <martin.kroening@eonerc.rwth-aachen.de>
> 
> Applied to target-arm.next, thanks.

FYI I was not ignoring this series, just postponed until freeze date,
and was looking at it earlier today. Interestingly this also fixes
my issues with m68k! So I'm glad to provide:

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>