Define the Typhoon class and instance initializers.

Add "cpu[*]" link properties in the instance_init of Typhoon.
Setting these cpu link properties will occur in a later commit.

Note: This is one step towards splitting typhoon_init() into the
instance_init and realize hooks. typhoon_init() currently takes
a fixed cpus array as a parameter; that array will be removed soon.

Signed-off-by: Yodel Eldar <yodel.eldar@yodel.dev>
---
 hw/alpha/typhoon.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index f392772500..5789829818 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -15,6 +15,7 @@
 #include "cpu.h"
 #include "hw/core/irq.h"
 #include "alpha_sys.h"
+#include "hw/core/qdev-properties.h"
 
 
 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
@@ -948,10 +949,32 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq,
     return b;
 }
 
+static void typhoon_pcihost_init(Object *obj)
+{
+    TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(obj);
+
+    int i;
+    for (i = 0; i < 4; ++i) {
+        g_autofree char *name = g_strdup_printf("cpu[%d]", i);
+        object_property_add_link(obj, name,  TYPE_ALPHA_CPU,
+                                 (Object **)&s->cchip.cpu[i],
+                                 qdev_prop_allow_set_link_before_realize, 0);
+    }
+}
+
+static void typhoon_pcihost_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->user_creatable = false;
+}
+
 static const TypeInfo typhoon_pcihost_info = {
     .name          = TYPE_TYPHOON_PCI_HOST_BRIDGE,
     .parent        = TYPE_PCI_HOST_BRIDGE,
     .instance_size = sizeof(TyphoonState),
+    .instance_init = typhoon_pcihost_init,
+    .class_init    = typhoon_pcihost_class_init,
 };
 
 static void typhoon_iommu_memory_region_class_init(ObjectClass *klass,

-- 
2.53.0

On 10/3/26 23:31, Yodel Eldar wrote:
> Define the Typhoon class and instance initializers.
> 
> Add "cpu[*]" link properties in the instance_init of Typhoon.
> Setting these cpu link properties will occur in a later commit.
> 
> Note: This is one step towards splitting typhoon_init() into the
> instance_init and realize hooks. typhoon_init() currently takes
> a fixed cpus array as a parameter; that array will be removed soon.
> 
> Signed-off-by: Yodel Eldar <yodel.eldar@yodel.dev>
> ---
>   hw/alpha/typhoon.c | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)


> +static void typhoon_pcihost_init(Object *obj)
> +{
> +    TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(obj);
> +
> +    int i;
> +    for (i = 0; i < 4; ++i) {
> +        g_autofree char *name = g_strdup_printf("cpu[%d]", i);
> +        object_property_add_link(obj, name,  TYPE_ALPHA_CPU,
> +                                 (Object **)&s->cchip.cpu[i],
> +                                 qdev_prop_allow_set_link_before_realize, 0);
> +    }
> +}

Hmm this machine is modelled using quite legacy style. The Typhoon
PCIHost object shouldn't have direct access to CPUs but only expose
IRQ lines, then the board layer wire these lines to CPUs.

Hi, Philippe! Thanks for commenting here and your review
of Patch 10.

On 11/03/2026 07:43, Philippe Mathieu-Daudé wrote:
> On 10/3/26 23:31, Yodel Eldar wrote:
>> Define the Typhoon class and instance initializers.
>>
>> Add "cpu[*]" link properties in the instance_init of Typhoon.
>> Setting these cpu link properties will occur in a later commit.
>>
>> Note: This is one step towards splitting typhoon_init() into the
>> instance_init and realize hooks. typhoon_init() currently takes
>> a fixed cpus array as a parameter; that array will be removed soon.
>>
>> Signed-off-by: Yodel Eldar <yodel.eldar@yodel.dev>
>> ---
>>   hw/alpha/typhoon.c | 23 +++++++++++++++++++++++
>>   1 file changed, 23 insertions(+)
> 
> 
>> +static void typhoon_pcihost_init(Object *obj)
>> +{
>> +    TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(obj);
>> +
>> +    int i;
>> +    for (i = 0; i < 4; ++i) {
>> +        g_autofree char *name = g_strdup_printf("cpu[%d]", i);
>> +        object_property_add_link(obj, name,  TYPE_ALPHA_CPU,
>> +                                 (Object **)&s->cchip.cpu[i],
>> +                                 
>> qdev_prop_allow_set_link_before_realize, 0);
>> +    }
>> +}
> 
> Hmm this machine is modelled using quite legacy style. The Typhoon
> PCIHost object shouldn't have direct access to CPUs but only expose
> IRQ lines, then the board layer wire these lines to CPUs.

Yeah, by inheritance the Typhoon is a PCI_HOST_BRIDGE, but
it's doing much more than that, so it's currently tightly
integrated with the CPUs.

I narrowly limited the scope of the series, so I hadn't even
considered decoupling the CPUs before your comment, but now
that I've been looking at it more closely: AFAICT there are
three nexuses we'd have to disentangle (please let me know
if I missed anything):
  (1) the CPU interrupts you mentioned
  (2) the timers that live in the CPUs (for now)
  (3) returning the cpu index when reading the MISC register

I think (1) and (2) are relatively straightforward: connect the
wires as you suggested with the IRQ handler in the cpu, and move
the timers into TyphoonState, respectively. (3)'s a bit trickier
IMHO: I suppose we could keep using current_cpu for (3) since
resolving (1) and (2) already lets us eliminate TyphoonState's
cchip.cpu, but it would be nice to remove that, too.
Open to suggestions. WDYT?

Thanks,
Yodel