On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
>
> According to the Zvfbfa ISA spec (v0.1), improperly NaN-boxed
> f-register operands must substitute the BF16 canonical NaN instead of
> the FP16 canonical NaN for some vector floating-point instructions.
>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
> target/riscv/translate.c | 8 ++++++++
> 2 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4df9a40b44..03ae85796a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2319,17 +2319,17 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)
> */
> static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
> {
> - switch (s->sew) {
> - case 1:
> - gen_check_nanbox_h(out, in);
> - break;
> - case 2:
> + if (s->sew == MO_16) {
> + if (s->altfmt) {
> + gen_check_nanbox_h_bf16(out, in);
> + } else {
> + gen_check_nanbox_h(out, in);
> + }
> + } else if (s->sew == MO_32) {
> gen_check_nanbox_s(out, in);
> - break;
> - case 3:
> + } else if (s->sew == MO_64) {
> tcg_gen_mov_i64(out, in);
> - break;
> - default:
> + } else {
> g_assert_not_reached();
> }
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 89d4f6fe67..d9df6a35ca 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -214,6 +214,14 @@ static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
> tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
> }
>
> +static void gen_check_nanbox_h_bf16(TCGv_i64 out, TCGv_i64 in)
> +{
> + TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
> + TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7fc0ull);
> +
> + tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
> +}
> +
> static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> {
> TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
> --
> 2.52.0
>
>