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[PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags

Max Chou posted 9 patches 3 weeks, 5 days ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
[PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags
Posted by Max Chou 3 weeks, 5 days ago 
We have more than 32-bits worth of state per TB, so use the
tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 include/exec/translation-block.h | 1 +
 target/riscv/cpu.h               | 3 +++
 target/riscv/tcg/tcg-cpu.c       | 7 ++++++-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
index 4f83d5bec9..40cc699031 100644
--- a/include/exec/translation-block.h
+++ b/include/exec/translation-block.h
@@ -65,6 +65,7 @@ struct TranslationBlock {
      * arm: an extension of tb->flags,
      * s390x: instruction data for EXECUTE,
      * sparc: the next pc of the instruction queue (for delay slots).
+     * riscv: an extension of tb->flags,
      */
     uint64_t cs_base;
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 962cc45073..4c0676ed53 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)
 FIELD(TB_FLAGS, PM_PMM, 29, 2)
 FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)
 
+FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)
+FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)
+
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 #else
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 720ff0c2a3..378b298886 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
     RISCVCPU *cpu = env_archcpu(env);
     RISCVExtStatus fs, vs;
     uint32_t flags = 0;
+    uint64_t ext_flags = 0;
     bool pm_signext = riscv_cpu_virt_mem_enabled(env);
 
     if (cpu->cfg.ext_zve32x) {
@@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
 
         /* lmul encoded as in DisasContext::lmul */
         int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
+        uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);
         uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
         uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
         uint32_t maxsz = vlmax << vsew;
@@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
         flags = FIELD_DP32(flags, TB_FLAGS, VMA,
                            FIELD_EX64(env->vtype, VTYPE, VMA));
         flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
+        ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt);
     } else {
         flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
     }
@@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
     flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
     flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
 
+    ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);
+
     return (TCGTBCPUState){
         .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,
         .flags = flags,
-        .cs_base = env->misa_ext,
+        .cs_base = ext_flags,
     };
 }
 
-- 
2.52.0
Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags
Posted by Alistair Francis 3 weeks, 2 days ago 
On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
>
> We have more than 32-bits worth of state per TB, so use the
> tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.
>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  include/exec/translation-block.h | 1 +
>  target/riscv/cpu.h               | 3 +++
>  target/riscv/tcg/tcg-cpu.c       | 7 ++++++-
>  3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
> index 4f83d5bec9..40cc699031 100644
> --- a/include/exec/translation-block.h
> +++ b/include/exec/translation-block.h
> @@ -65,6 +65,7 @@ struct TranslationBlock {
>       * arm: an extension of tb->flags,
>       * s390x: instruction data for EXECUTE,
>       * sparc: the next pc of the instruction queue (for delay slots).
> +     * riscv: an extension of tb->flags,
>       */
>      uint64_t cs_base;
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 962cc45073..4c0676ed53 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)
>  FIELD(TB_FLAGS, PM_PMM, 29, 2)
>  FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)
>
> +FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)
> +FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)
> +
>  #ifdef TARGET_RISCV32
>  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>  #else
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 720ff0c2a3..378b298886 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>      RISCVCPU *cpu = env_archcpu(env);
>      RISCVExtStatus fs, vs;
>      uint32_t flags = 0;
> +    uint64_t ext_flags = 0;
>      bool pm_signext = riscv_cpu_virt_mem_enabled(env);
>
>      if (cpu->cfg.ext_zve32x) {
> @@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>
>          /* lmul encoded as in DisasContext::lmul */
>          int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
> +        uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);
>          uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
>          uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
>          uint32_t maxsz = vlmax << vsew;
> @@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>          flags = FIELD_DP32(flags, TB_FLAGS, VMA,
>                             FIELD_EX64(env->vtype, VTYPE, VMA));
>          flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
> +        ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt);
>      } else {
>          flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
>      }
> @@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>      flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
>      flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
>
> +    ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);
> +
>      return (TCGTBCPUState){
>          .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,
>          .flags = flags,
> -        .cs_base = env->misa_ext,
> +        .cs_base = ext_flags,

We need to update the comment in `struct TranslationBlock` for
`target_ulong cs_base`

Alistair

>      };
>  }
>
> --
> 2.52.0
>
>
Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags
Posted by Max Chou 2 weeks, 6 days ago 
On 2026-03-09 15:01, Alistair Francis wrote:
> On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
> >
> > We have more than 32-bits worth of state per TB, so use the
> > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.
> >
> > Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> > Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> >  include/exec/translation-block.h | 1 +
> >  target/riscv/cpu.h               | 3 +++
> >  target/riscv/tcg/tcg-cpu.c       | 7 ++++++-
> >  3 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
> > index 4f83d5bec9..40cc699031 100644
> > --- a/include/exec/translation-block.h
> > +++ b/include/exec/translation-block.h
> > @@ -65,6 +65,7 @@ struct TranslationBlock {
> >       * arm: an extension of tb->flags,
> >       * s390x: instruction data for EXECUTE,
> >       * sparc: the next pc of the instruction queue (for delay slots).
> > +     * riscv: an extension of tb->flags,
> >       */
> >      uint64_t cs_base;
> >
>

Hi Alistair,

I’m curious to know if you mean adding more details here, such as
specifying the bit width for misa (e.g., 32 bits) or the bit width for
ALTFMT (e.g., 1 bit).
If so, I’ll include these details in the v6 version.

Thanks,
rnax

> We need to update the comment in `struct TranslationBlock` for
> `target_ulong cs_base`
> 
> Alistair
>
Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags
Posted by Alistair Francis 2 weeks, 6 days ago 
On Thu, Mar 12, 2026 at 9:42 PM Max Chou <max.chou@sifive.com> wrote:
>
> On 2026-03-09 15:01, Alistair Francis wrote:
> > On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
> > >
> > > We have more than 32-bits worth of state per TB, so use the
> > > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.
> > >
> > > Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> > > Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> > > Signed-off-by: Max Chou <max.chou@sifive.com>
> > > ---
> > >  include/exec/translation-block.h | 1 +
> > >  target/riscv/cpu.h               | 3 +++
> > >  target/riscv/tcg/tcg-cpu.c       | 7 ++++++-
> > >  3 files changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
> > > index 4f83d5bec9..40cc699031 100644
> > > --- a/include/exec/translation-block.h
> > > +++ b/include/exec/translation-block.h
> > > @@ -65,6 +65,7 @@ struct TranslationBlock {
> > >       * arm: an extension of tb->flags,
> > >       * s390x: instruction data for EXECUTE,
> > >       * sparc: the next pc of the instruction queue (for delay slots).
> > > +     * riscv: an extension of tb->flags,
> > >       */
> > >      uint64_t cs_base;
> > >
> >
>
> Hi Alistair,
>
> I’m curious to know if you mean adding more details here, such as
> specifying the bit width for misa (e.g., 32 bits) or the bit width for
> ALTFMT (e.g., 1 bit).
> If so, I’ll include these details in the v6 version.

Oh! You did update the comment. Sorry I missed that.

No action required!

Alistair

>
> Thanks,
> rnax
>
> > We need to update the comment in `struct TranslationBlock` for
> > `target_ulong cs_base`
> >
> > Alistair
> >

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