This patch seriers add a new model for Cadence GPIO controller which
supports 32 pins and interrupts for level-triggered/edge-triggered type on
input pins.

Also define new trace functions for analysis purpose and new configuration to
enable this model.

Kuan-Jui Chiu (1):
  hw/gpio: Add Cadence GPIO model

 hw/gpio/Kconfig                |   3 +
 hw/gpio/cadence_gpio.c         | 312 +++++++++++++++++++++++++++++++++
 hw/gpio/meson.build            |   1 +
 hw/gpio/trace-events           |   5 +
 include/hw/gpio/cadence_gpio.h |  66 +++++++
 5 files changed, 387 insertions(+)
 create mode 100644 hw/gpio/cadence_gpio.c
 create mode 100644 include/hw/gpio/cadence_gpio.h

-- 
2.34.1

On Thu, 5 Mar 2026 at 10:39, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>
> This patch seriers add a new model for Cadence GPIO controller which
> supports 32 pins and interrupts for level-triggered/edge-triggered type on
> input pins.
>
> Also define new trace functions for analysis purpose and new configuration to
> enable this model.
>
> Kuan-Jui Chiu (1):
>   hw/gpio: Add Cadence GPIO model
>
>  hw/gpio/Kconfig                |   3 +
>  hw/gpio/cadence_gpio.c         | 312 +++++++++++++++++++++++++++++++++
>  hw/gpio/meson.build            |   1 +
>  hw/gpio/trace-events           |   5 +
>  include/hw/gpio/cadence_gpio.h |  66 +++++++
>  5 files changed, 387 insertions(+)

Hi; this patch adds a new TYPE_SYSBUS (memory-mapped) device,
but it doesn't add that new device to any board models, so
this is dead code, as it stands.

What's the intended user? Generally we recommend adding
new devices to QEMU along with the machine/SoC/whatever
that uses them.

thanks
-- PMM

Hi

Understood.
I verified this device model with our Axiado EVK machine which is still 
under development
Does that mean I have to submit patch to add our EVK machine into QEMU 
first then add this device to it?

B.R.
Howard Chiu
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Thu, 5 Mar 2026 at 10:39, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>> This patch seriers add a new model for Cadence GPIO controller which
>> supports 32 pins and interrupts for level-triggered/edge-triggered type on
>> input pins.
>>
>> Also define new trace functions for analysis purpose and new configuration to
>> enable this model.
>>
>> Kuan-Jui Chiu (1):
>>    hw/gpio: Add Cadence GPIO model
>>
>>   hw/gpio/Kconfig                |   3 +
>>   hw/gpio/cadence_gpio.c         | 312 +++++++++++++++++++++++++++++++++
>>   hw/gpio/meson.build            |   1 +
>>   hw/gpio/trace-events           |   5 +
>>   include/hw/gpio/cadence_gpio.h |  66 +++++++
>>   5 files changed, 387 insertions(+)
> Hi; this patch adds a new TYPE_SYSBUS (memory-mapped) device,
> but it doesn't add that new device to any board models, so
> this is dead code, as it stands.
>
> What's the intended user? Generally we recommend adding
> new devices to QEMU along with the machine/SoC/whatever
> that uses them.
>
> thanks
> -- PMM

On Thu, 5 Mar 2026 at 11:22, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>
> Hi
>
> Understood.
> I verified this device model with our Axiado EVK machine which is still
> under development
> Does that mean I have to submit patch to add our EVK machine into QEMU
> first then add this device to it?

Yes, that's generally the way we would prefer. Or if this
device is used in some existing board we already model
(and we just haven't implemented it there) then that would
be the other option.

thanks
-- PMM

Understood.


I did not find any existing device trees in current upstream kernel 
using Cadence GPIO except for our EVK
So I would submit another patch to QEMU for our EVK machine then update 
this patch

B.R.
Howard Chiu
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Thu, 5 Mar 2026 at 11:22, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>> Hi
>>
>> Understood.
>> I verified this device model with our Axiado EVK machine which is still
>> under development
>> Does that mean I have to submit patch to add our EVK machine into QEMU
>> first then add this device to it?
> Yes, that's generally the way we would prefer. Or if this
> device is used in some existing board we already model
> (and we just haven't implemented it there) then that would
> be the other option.
>
> thanks
> -- PMM