hw/net/xilinx_axienet.c: Prevent writes to PHY Identification registers

[PATCH] hw/net/xilinx_axienet.c: Prevent writes to PHY Identification registers

Posted by Jim MacArthur 1 month, 1 week ago

There are other registers in the PHY model which should be partially or
entirely read-only, but this solves the immediate issue.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3297

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
See:

https://gitlab.com/qemu-project/qemu/-/issues/3297

https://lore.kernel.org/qemu-devel/CAJy5ezqTAMr=A3uAfmuWLepK66AdLRu4Q8AmFMh4+4q2HtDrkA@mail.gmail.com/

IEEE 802.3-2022 does not explicitly state that these registers
should be read-only, but suggests it in 22.2.4.3.1 which says this
information should be entirely manufacturer-supplied information.

The standard does mention several other registers in the set which
should be partially or entirely read-only, so further work may be
required.
---
 hw/net/xilinx_axienet.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index d85f8bb23f..970732b162 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -141,6 +141,10 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
     regnum = req & 0x1f;
     DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
     switch (regnum) {
+        case 2:
+        case 3:
+            /* Writes to PHY Identification registers are disallowed */
+            break;
         default:
             phy->regs[regnum] = data;
             break;

---
base-commit: 3fb456e9a0e9eef6a71d9b49bfff596a0f0046e9
change-id: 20260305-xilinx-phy-protection-c396a658d072

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>

Re: [PATCH] hw/net/xilinx_axienet.c: Prevent writes to PHY Identification registers

Posted by Philippe Mathieu-Daudé 1 month ago

On 5/3/26 13:13, Jim MacArthur wrote:
> There are other registers in the PHY model which should be partially or
> entirely read-only, but this solves the immediate issue.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3297
> 
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---


> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index d85f8bb23f..970732b162 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -141,6 +141,10 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
>       regnum = req & 0x1f;
>       DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
>       switch (regnum) {
> +        case 2:
> +        case 3:
> +            /* Writes to PHY Identification registers are disallowed */
> +            break;
>           default:
>               phy->regs[regnum] = data;
>               break;

Checkpatch.pl complains for pre-existing coding style:

ERROR: switch and case should be at the same indent
#27: FILE: hw/net/xilinx_axienet.c:143:
      switch (regnum) {
+        case 2:
+        case 3:

total: 1 errors, 0 warnings, 10 lines checked

Anyway, queued, thanks!

Re: [PATCH] hw/net/xilinx_axienet.c: Prevent writes to PHY Identification registers

Posted by Edgar E. Iglesias 1 month, 1 week ago

On Thu, Mar 5, 2026 at 6:13 AM Jim MacArthur <jim.macarthur@linaro.org>
wrote:

> There are other registers in the PHY model which should be partially or
> entirely read-only, but this solves the immediate issue.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3297
>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>




> ---
> See:
>
> https://gitlab.com/qemu-project/qemu/-/issues/3297
>
>
> https://lore.kernel.org/qemu-devel/CAJy5ezqTAMr=A3uAfmuWLepK66AdLRu4Q8AmFMh4+4q2HtDrkA@mail.gmail.com/
>
> IEEE 802.3-2022 does not explicitly state that these registers
> should be read-only, but suggests it in 22.2.4.3.1 which says this
> information should be entirely manufacturer-supplied information.
>
> The standard does mention several other registers in the set which
> should be partially or entirely read-only, so further work may be
> required.
> ---
>  hw/net/xilinx_axienet.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index d85f8bb23f..970732b162 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -141,6 +141,10 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned
> int data)
>      regnum = req & 0x1f;
>      DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
>      switch (regnum) {
> +        case 2:
> +        case 3:
> +            /* Writes to PHY Identification registers are disallowed */
> +            break;
>          default:
>              phy->regs[regnum] = data;
>              break;
>
> ---
> base-commit: 3fb456e9a0e9eef6a71d9b49bfff596a0f0046e9
> change-id: 20260305-xilinx-phy-protection-c396a658d072
>
> Best regards,
> --
> Jim MacArthur <jim.macarthur@linaro.org>
>
>