Hi Max,
On Wed, Mar 04, 2026 at 09:39:52PM +0800, Max Chou wrote:
> This patchset adds support for the RISC-V Zvfofp8min and Zvfofp4min isa
> extensions that provide conversion operations for OCP FP8/FP4 formats.
>
> * Zvfofp8min (Version 0.2.1):
> The Zvfofp8min extension provides minimal vector conversion support
> for OFP8 formats. It requires the Zve32f extension and leverages the
> altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between
> E4M3 (altfmt=0) and E5M2 (altfmt=1) formats.
> - Canonical NaN for both E4M3 and E5M2 is 0x7f
> - All NaNs are treated as quiet NaNs
> Instructions added/extended:
> - vfwcvtbf16.f.f.v: OFP8 to BF16 widening conversion
> - vfncvtbf16.f.f.w: BF16 to OFP8 narrowing conversion
> - vfncvtbf16.sat.f.f.w: BF16 to OFP8 with saturation (new)
> - vfncvt.f.f.q: FP32 to OFP8 quad-narrowing conversion (new)
> - vfncvt.sat.f.f.q: FP32 to OFP8 with saturation (new)
>
> * Zvfofp4min (Version 0.1):
> The Zvfofp4min extension provides minimal vector conversion support
> for the OFP4 E2M1 format. It requires the Zve32f extension.
> Instructions added:
> - vfext.vf2: OFP4 E2M1 to OFP8 E4M3 widening conversion
>
> Chagnes in v4
> - Rebase on riscv-to-apply.next (commit 21101a7)
> - Remove the softfloat library related patches (Thanks for RH's help to
> split this part)
> - Add missing illegal ALTFMT SEW pattern checking for Zvfofp8min in
> patch 4 (target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
> conversion for Zvfofp8min extension)
>
Thanks for this v4 series! I learned a lot about the OCP
FP8/FP4 formats and the Zvfofp8min/Zvfofp4min extensions
while reviewing these patches.
I've been preparing an RFC patchset that provides basic
tests for the OCP FP8/FP4 specification, to complement
QEMU's existing fp test coverage. It's not quite ready
yet, but I plan to post it upstream soon for discussion.
A few minor issues noted in individual patch replies
(missing REQUIRE_FPU in patch 12, typos in commit
subjects). Otherwise the series looks good overall.
Thanks,
Chao
> Changes in v3
> - Add floatN_nan_is_snan to simply the quiet/signaling NaN checking flow
> in patch 2 & 3
> - Add patch 4 to fix pseudo-NaN handling in FPATAN/FYL2XP1/FYL2X helpers
>
> Changes in v2
> - Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4
> - Added new v2 patch 2 to refactor the IEEE format NaN classification
> functions (float16, bfloat16, float32, float64) to use internal helper
> functions, reducing code duplication and improving maintainability.
> The OCP FP8 NaN classification functions follow the same pattern.
> - Refactored softfloat implementation to use capability-based FloatFmt
> flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max)
> instead of monolithic flags
> - Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags
> from float_status; now using local float_status with no_signaling_nans
> and default_nan_pattern for RISC-V Zvfofp8min instructions
> - Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset
>
> v3: <20260204051756.667397-1-max.chou@sifive.com>
> v2: <20260127063723.442734-1-max.chou@sifive.com>
> v1: <20260108151650.16329-1-max.chou@sifive.com>
>
> References
> * OCP FP8 specification:
> https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1
> * Zvfofp8min specification (v0.2.1 commit e1e20a7):
> https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc
> * Zvfofp4min specification (v0.1 commit e1e20a7):
> https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp4min.adoc
>
> Based-on: <20260304132514.2889449-1-max.chou@sifive.com>
> ([v4,0/9] Add Zvfbfa extension support)
> Based-on: <20260226071817.1417875-1-max.chou@sifive.com>
> ([v2,0/2] fpu: Fix OCP FP8 E4M3 conversion issues)
>
> rnax
>
>
> Max Chou (14):
> target/riscv: rvv: Fix NOP_UU_B vs2 width
> target/riscv: Add cfg properity for Zvfofp8min extension
> target/riscv: Add implied rules for Zvfofp8min extension
> target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
> conversion for Zvfofp8min extension
> target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8
> conversion for Zvfofp8min extension
> target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min
> extension
> target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions
> for Zvfofp8min extension
> target/riscv: Expose Zvfofp8min properity
> disas/riscv: Add support of Zvfofp8min extension
> target/riscv: Add cfg properity for Zvfofp4min extension
> target/riscv: Add implied rules for Zvfofp4min extension
> target/riscv: rvv: Add vfext.vf2 instruction for Zvfofp4min extension
> target/riscv: Expose Zvfofp4min properity
> disas/riscv: Add support of Zvfofp4min extension
>
> disas/riscv.c | 12 ++
> target/riscv/cpu.c | 29 ++++-
> target/riscv/cpu_cfg_fields.h.inc | 2 +
> target/riscv/helper.h | 15 +++
> target/riscv/insn32.decode | 8 ++
> target/riscv/insn_trans/trans_rvbf16.c.inc | 32 +++--
> target/riscv/insn_trans/trans_rvofp4.c.inc | 43 +++++++
> target/riscv/insn_trans/trans_rvofp8.c.inc | 105 ++++++++++++++++
> target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++
> target/riscv/tcg/tcg-cpu.c | 10 ++
> target/riscv/translate.c | 2 +
> target/riscv/vector_helper.c | 137 ++++++++++++++++++++-
> 12 files changed, 421 insertions(+), 13 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvofp4.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc
>
> --
> 2.52.0
>