RISC-V Zbr0p93 extension

[PATCH 0/3] RISC-V Zbr0p93 extension

James Wainwright posted 3 patches 1 month, 1 week ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260304121113.117299-1-james.wainwright@lowrisc.org

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

MAINTAINERS                               |  2 +-
disas/meson.build                         |  3 +-
disas/riscv-zbr.c                         | 78 +++++++++++++++++++++
disas/riscv-zbr.h                         | 18 +++++
disas/riscv.c                             |  4 ++
include/qemu/crc32.h                      | 18 +++++
include/qemu/crc32c.h                     |  1 +
target/riscv/bitmanip_helper.c            | 20 ++++++
target/riscv/cpu.c                        |  4 +-
target/riscv/cpu_cfg.h                    |  3 +
target/riscv/cpu_cfg_fields.h.inc         |  1 +
target/riscv/helper.h                     |  2 +
target/riscv/insn32.decode                | 12 ++++
target/riscv/insn_trans/trans_rvb.c.inc   | 37 ++++++++++
tests/tcg/riscv64/Makefile.softmmu-target |  5 ++
tests/tcg/riscv64/test-crc32.S            | 64 +++++++++++++++++
util/crc32.c                              | 85 +++++++++++++++++++++++
util/crc32c.c                             |  4 +-
util/meson.build                          |  1 +
19 files changed, 357 insertions(+), 5 deletions(-)
create mode 100644 disas/riscv-zbr.c
create mode 100644 disas/riscv-zbr.h
create mode 100644 include/qemu/crc32.h
create mode 100644 tests/tcg/riscv64/test-crc32.S
create mode 100644 util/crc32.c

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[PATCH 0/3] RISC-V Zbr0p93 extension

Posted by James Wainwright 1 month, 1 week ago

This patch series adds support for the unratified RISC-V Zbr0p93
extension which is implemented by the Ibex core and used in the (now
taped-out) OpenTitan mask ROM.

Because this extension uses the standard reserved encoding space, it's
possible that it could conflict with a ratified extension in the future.

These patches were written by Rivos for the OpenTitan fork of QEMU, but
lowRISC is choosing to upstream them.

Emmanuel Blot (3):
  util: export CRC32[C] lookup tables
  target/riscv: add unratified RISC-V Zbr0p93 ext
  disas: diassemble RISC-V Zbr0p93 instructions

 MAINTAINERS                               |  2 +-
 disas/meson.build                         |  3 +-
 disas/riscv-zbr.c                         | 78 +++++++++++++++++++++
 disas/riscv-zbr.h                         | 18 +++++
 disas/riscv.c                             |  4 ++
 include/qemu/crc32.h                      | 18 +++++
 include/qemu/crc32c.h                     |  1 +
 target/riscv/bitmanip_helper.c            | 20 ++++++
 target/riscv/cpu.c                        |  4 +-
 target/riscv/cpu_cfg.h                    |  3 +
 target/riscv/cpu_cfg_fields.h.inc         |  1 +
 target/riscv/helper.h                     |  2 +
 target/riscv/insn32.decode                | 12 ++++
 target/riscv/insn_trans/trans_rvb.c.inc   | 37 ++++++++++
 tests/tcg/riscv64/Makefile.softmmu-target |  5 ++
 tests/tcg/riscv64/test-crc32.S            | 64 +++++++++++++++++
 util/crc32.c                              | 85 +++++++++++++++++++++++
 util/crc32c.c                             |  4 +-
 util/meson.build                          |  1 +
 19 files changed, 357 insertions(+), 5 deletions(-)
 create mode 100644 disas/riscv-zbr.c
 create mode 100644 disas/riscv-zbr.h
 create mode 100644 include/qemu/crc32.h
 create mode 100644 tests/tcg/riscv64/test-crc32.S
 create mode 100644 util/crc32.c

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2.48.1