hw/riscv/riscv-iommu: Bug fixes and IPSR.PMIP support

[PATCH 0/2] hw/riscv/riscv-iommu: Bug fixes and IPSR.PMIP support

Jay Chang posted 2 patches 1 month, 1 week ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260304040959.47267-1-jay.chang@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

hw/riscv/riscv-iommu-bits.h | 1 +
hw/riscv/riscv-iommu-hpm.c  | 1 +
hw/riscv/riscv-iommu.c      | 4 ++++
3 files changed, 6 insertions(+)

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[PATCH 0/2] hw/riscv/riscv-iommu: Bug fixes and IPSR.PMIP support

Posted by Jay Chang 1 month, 1 week ago

This series contains two fixes for the RISC-V IOMMU implementation:

1. Fix a bug in the HPM (Hardware Performance Monitor) timer setup where
   irq_overflow_left was not properly reset, causing stale values from
   previous timer setups to affect new timer behavior.

2. Add proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP
   (Performance Monitor Interrupt Pending) bit, which was missing from
   the IPSR register implementation.

Jay Chang (2):
  hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug
  hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support

 hw/riscv/riscv-iommu-bits.h | 1 +
 hw/riscv/riscv-iommu-hpm.c  | 1 +
 hw/riscv/riscv-iommu.c      | 4 ++++
 3 files changed, 6 insertions(+)

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2.48.1