On Wed, Mar 4, 2026 at 1:09 PM Jay Chang <jay.chang@sifive.com> wrote:
>
> Ensure that the 'done' bit is set upon transfer completion, even if
> an error occurs, since all transfers are considered completed regardless
> of success or failure.
>
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/dma/sifive_pdma.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
> index 6d06ec0375..7b22e51492 100644
> --- a/hw/dma/sifive_pdma.c
> +++ b/hw/dma/sifive_pdma.c
> @@ -153,6 +153,7 @@ done:
> error:
> s->chan[ch].state = DMA_CHAN_STATE_ERROR;
> s->chan[ch].control |= CONTROL_ERR;
> + s->chan[ch].control |= CONTROL_DONE;
> }
>
> static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
> --
> 2.48.1
>
>